1
PS8327 09/14/98
Product Description
Pericom Semiconductor's PI74VCX series of logic circuits are
produced in the Company's advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74VCX16374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit Flip-Flops or one
16-bit flip-flop. On the positive transition of the clock (CLK)
input, the Q outputs of the flip-flop take on the logic levels set up
at the date (D) inputs.
A buffered Output Enable (OE) input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state in which the outputs neither load
nor drive the bus lines significantly. The high-impedance state
and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not
affect internal operations of the flip-flop. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
The PI74VCX family is I/O Tolerant, allowing it to operate in
mixed 1.8V/3.6V systems.
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PI74VCX16374
16-Bit D-Type Flip-Flop
with 3-STATE Outputs
Logic Block Diagram
Product Features
The PI74VCX Family is designed for low voltage
operation, V
DD
= 1.8V to 3.6V
3.6V I/O Tolerant Inputs and Outputs
Supports Live Insertion
Balanced Drive, 24mA
Uses patented Noise Reduction Circuitry
Typical V
OLP
(Output Ground Bounce)
< 0.6V at V
DD
= 2.5V, T
A
= 25C
Typical V
OHV
(Output V
OH
Undershoot)
< -0.6V at V
DD
= 2.5V, T
A
= 25C
Power-Off high impedance inputs and outputs
Industrial operation at 40C to +85C
Packages available:
48-pin 240 mil. wide plastic TSSOP (A)
48-pin 300 mil. wide plastic SSOP (V)
1CLK
1Q1
1D
>C1
1D1
To Seven Other Channels
1OE
1
48
47
2
2CLK
2Q1
2D1
To Seven Other Channels
25
36
13
24
2OE
1D
>C1
2
PS8327 09/14/98
PI74VCX16374
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16-Bit D-Type Flip-Flop with 3-State Outputs
s
t
u
p
n
I
s
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u
p
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u
O
E
O
K
L
C
D
Q
L
H
H
L
L
L
L
L
r
o
H
X
Q
0
H
X
X
Z
Product Pin Description
Truth Table
(1)
Notes:
1.
H = High Signal Level
L = Low Signal Level
X = Don't Care or Irrelevant
Z = High Impedance
Product Pin Configuration
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
2
3
4
5
6
7
8
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
32
31
30
29
28
27
26
25
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
48-PIN
A48
V48
Pin Name
Description
OE
Output Enable Input (Active LOW)
CLK
Clock Input
Dx
Data Inputs
Qx
3-State Outputs
GND
Ground
V
CC
Power
3
PS8327 09/14/98
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PI74VCX16374
16-Bit D-Type Flip-Flop with 3-State Outputs
Recommended Operating Conditions
(2)
Notes:
1. Absolute maximum of I
O
must be observed.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, V
DD
= 3.0V.
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3
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2
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2
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8
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1
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8
C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
f
o
r
extended periods may affect reliability.
Supply Voltage Range, V
DD ................................................
0.5V to 4.6V
Input Voltage Range, V
I .........................................................
-0.5V to 4.6V
Output Voltage Range, V
O
(3-Stated) .......................... -0.5V to 4.6V
Output Voltage Range, V
O
(1)
(Active) ............ 0.5V to V
DD
+ 0.5V
DC Input Diode Current (I
IK
) V
I
< 0V .................................... -50mA
DC Output Diode Current (I
OK
)
V
O
< 0V ................................................................................ -50mA
V
O
> V
DD ............................................................................................
-50mA
DC Output Source/Sink Current (I
OH
/I
OL
) ............................ 50mA
DC V
DD
or GND Current per Supply Pin (I
CC
or GND) .... 100mA
Storage Temperature Range, T
STG
............................ 65
C to150
C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
4
PS8327 09/14/98
PI74VCX16374
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16-Bit D-Type Flip-Flop with 3-State Outputs
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1
7
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2
2
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=
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2
4
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3
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=
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0
5
7
Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
DC Characteristics (2.7V < V
DD
3.6V)
5
PS8327 09/14/98
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PI74VCX16374
16-Bit D-Type Flip-Flop with 3-State Outputs
DC Characteristics
(2.3V
V
DD
2.7V)
DC Characteristics
(1.8V
V
DD
2.3V)
Note:
1. Not guaranteed
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8
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1
0
2
6
PS8327 09/14/98
PI74VCX16374
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16-Bit D-Type Flip-Flop with 3-State Outputs
Dynamic Switching Characteristics
AC Electrical Characteristics
Notes:
1. For C
L
=
50pF add approximatly 300ps to AC maximum specification.
2. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same
device. The specification applies to any outputs switching in the same direction, either HIGH or LOW (t
OSHL
)
or LOW to HIGH (t
OSLH
).
AC Setup Requirements
Capacitance
l
o
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D
D
T
A
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T
C
5
2
+
=
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ei
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L
O
C
L
F
p
0
5
=
V
H
I
V
=
D
D
V
L
I
V
0
=
8
.
1
5
.
2
3
.
3
5
2
.
0
6
.
0
8
.
0
V
V
P
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PS8327 09/14/98
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74VCX16374
16-Bit D-Type Flip-Flop with 3-State Outputs
Test Circuits and Switching Waveforms
Parameter Measurement Information (V
DD
= 1.8V - 3.6V)
Setup, Hold, and Release Timing
Pulse Width
Switch Position
Propagaton Delay
Enable Disable Timing
Data
Input
t
H
V
DD
t
SU
0V
Timing
Input
V
DD
0V
V
DD/2
V
DD/2
Low-High-Low
Pulse
t
W
High-Low-High
Pulse
V
DD
0V
V
DD
0V
V
DD/2
V
DD/2
Input
Opposite Phase
Input Transition
t
PLH
t
PHL
t
PLH
t
PHL
V
DD
0V
V
DD
V
OL
V
DD
0V
Output
V
DD/2
V
DD/2
V
DD/2
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
Output
Control
(Active LOW)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PLZ
V
DD
0V
V
DD
V
OL
0V
Output
Waveform 1
S1 at 2xV
DD
(see Note B)
+0.15V
-0.15V
V
OH
V
DD
t
PHZ
t
PZH
V
DD/2
V
DD/2
V
DD
/2
C
L
R
1
500
30pF
From Output
Under Test
GND
2 x V
DD
Open
(See Note A)
R
L
500
t
s
e
T
1
S
t
D
P
n
e
p
O
t
Z
L
P
/t
L
Z
P
x
2 V
D
D
t
Z
H
P
/t
H
Z
P
D
N
G
Notes:
A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that
the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is HIGH except when disabled by the output
control.
C. All input pulses are supplied by generators having the follow
ing characteristics:
P
RR
10 MHz, Z
O
= 50
,
t
R
2ns,
t
F
2ns,
measured from 10% to 90%, unless otherwise specified.
D. The outputs are measured one at a time with one transition per
measurement.
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