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PS8641 10/14/04
Features
IEEE 802.3z Gigabit Ethernet Compliant
Supports 1.25 Gbps Using NRZ Coding over uncompensated
twin coax cable
Fully integrated CMOS IC
Low Power Consumption
ESD rating >2000V (Human Body Model) or > 200V (Ma-
chine Model)
5-Volt Input Tolerance
Pin-Compatible with Agilent HDMP1636A/HDMP- 1646A
and Vitesse VSC7123 transceivers (see Appendix A)
Packaging (Pb-free & Green available):
- 64-pin LQFP (FC)
- 64-pin LQFP (FD)
Applications
Gigabit Ethernet
Serial Backplane
Proprietary point-to-point applicaitons
Description
The PI90SD1636A is a single chip, Gigabit Ethernet transceiver.
It performs all the functions of the Physical Medium Attachment
(PMA) portion of the Physical layer, as specified by the IEEE
802.3z Gigabit Ethernet standard. These functions include parallel-
to-serial and serial-to-parallel conversion, clock generation, clock
data recovery, and word synchronization. In addition, an internal
loopback function is provided for system debugging.
The PI90SD1636A is ideal for Gigabit Ethernet, serial backplane
and proprietary point-to-point applications. The device sup-
ports 1000BASE-LX and 1000BASE-SX fiber-optic media, and
1000BASE-CX copper media.
The transmitter section of the PI90SD1636A accepts 10-bit wide
parallel TTL data and converts it to a high speed serial data stream.
The parallel data is encoded in 8b/10b format. This incoming
parallel data is latched into an input register, and synchronized
on the rising edge of the 125 MHz reference clock supplied by
the user. A phase locked loop (PLL) locks to the 125 MHz clock.
The clock is then multiplied by 10 to produce a 1.25 GHz serial
clock that is used to provide the high speed serial data output. The
output is sent through a Pseudo Emitter Coupled Logic (PECL)
driver. This output connects directly to a copper cable in the case
of 1000BASE-CX medium, or to a fiber optic module in the case
of 1000BASE-LX or 1000BASE SX fiber optic medium.
The receiver section of the PI90SD1636A accepts a serial PECL-
compatible data stream at a 1.25 Gbps rate, recovers the original
10-bit wide parallel data format, and retimes the data. A PLL locks
onto the incoming serial data stream, and recovers the 1.25 GHz
high speed serial clock and data. This is accomplished by con-
tinually frequency locking onto the 125 MHz reference clock, and
by phase locking onto the incoming data stream. The serial data
is converted back to parallel data format. The `comma' character
is used to establish byte alignment. Two 62.5 MHz clocks, 180
degrees out of phase, are recovered. These clocks are alternately
used to clock out the parallel data on the rising edge. This parallel
data is sent to the user in TTL-compatible form.
PI90SD1636A
SERDES Gigabit Ethernet Transceiver
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PS8641 10/14/04
PI90SD1636A
SERDES Gigabit Ethernet Transceiver
Table 2. Pin Description
Name
Pin #
Type
Description
GND_ESD
VCC_ESD
1, 14
5, 10
P
Power and ground pairs for pad ESD structure.
TX<0>
TX<1>
TX<2>
TX<3>
TX<4>
TX<5>
TX<6>
TX<7>
TX<8>
TX<9>
2
3
4
6
7
8
9
11
12
13
TTL_IN 0-bit parallel data input pins. This data should be 10b/8b encoded. The least
significant bit is TX<0> and is transmitted first.
GND_TXA
VCC_TXA
15
18
P
Power and ground pair for TX PLL analog circuits.
NC
16, 17,27,
48, 49
NC
No Connect
EWRAP
19
TTL_IN
Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial data
are internally wrapped from the transmitter serial data output back to the receiver
data input. Also, when asserted, DOUT are held static at logic 1. When deasserted,
DOUT and .DIN are active.
VCC_TXD
GND_TXD
20
21
P
Power and ground pair for TX digital circuits.
TX_CLK
22
TTL_IN
Reference clock and transmit byte clock. This is a 125 MHz system clock supplied
by the host system. On the positive edge of the clock, the input data, TX<9:0>, are
latched into the register. This clock is multiplied by 10 internally, to generate the
transmit serial bit clock.
VCC_RXD
GND_RXD
23 28,
25
P
Power and ground pair for digital circuits in the receiver portion.
EN_CDET
24
TTL_IN
Comma Detect Enable. This pin is active HIGH. When asserted, the internal byte
alignment function is turned on, to allow the clock to synchronize with the comma
character (0011111XXX). When de-asserted, the function is disabled and will not align
the clock and data. In this mode COM_DET is set to LOW.
SIG_DET
26
TTL_
OUT
Signal Detect. This pin is active HIGH. It indicates the loss of input signal on the
high-speed serial inputs, DIN. SIG_DET is set to LOW when differential inputs are
less than 50 mV.
VCC_RX
GND_RX
29
32
P
Power and ground pair for the clock signal of the receiver portion.
RX_CLK<1>
RX_CLK<0>
30
31
TTL_
OUT
Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals that are
recovered by the receiver section. The received bytes are alternately clocked by the
rising edges of these signals. The rising edge of RX_CLK<1> aligns with a comma
character when detected.
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PS8641 10/14/04
PI90SD1636A
SERDES Gigabit Ethernet Transceiver
Table 2. Pin Description (Continued.)
Name
Pin#
Type
Description
GND_RXT
VCC_RXT
33 46,
37, 42
P
Power and ground pairs for ESD structure.
RX<9>
RX<8>
RX<7>
RX<6>
RX<5>
RX<4>
RX<3>
RX<2>
RX<1>
RX<0>
34
35
36
37
38
39
40
41
43
44
45
TTL_OUT
Received Parallel Data Output. RX<0> is the least significant bit and is
received first. When DIN lose input data, all RX pins will be held HIGH.
COM_DET
47
TTL_OUT
Comma detect. This pin is active HIGH. When asserted, it indicates the
detection of comma character (0011111XXX). It is active only when EN_CEDT
is enabled.
VCC_RXF
GND_RXF
50
51
P
Power and ground pair for the front-end of the receiver section.
DIN-
52
HS_IN
High-speed serial data input. Serial data input is received when
DIN+
54
EWRAP is disabled.
VCC_RXESD
GND_RXESD
53,55
56
P
Power and ground pair for ESD structure.
VCC_RXA
GND_RXA
57, 59
58
P
Power and ground pair for analog circuits of the receiver section.
VCC_TX_ECL
60
P
Power supply to line driver circuits. Ground supply is from pin 64.
DOUT-
DOUT+
61
62
HS_OUT
High-speed serial data output. These pins are active when EWRAP is disabled
and are held static at logic 1 when EWRAP is enable.
VCC_TX_HS
GND_TX_HS
63
64
P
Power and ground pair for high-speed transmit logic in the parallel-to-serial
section.
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