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Электронный компонент: 74AHC132D

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DATA SHEET
Product specification
Supersedes data of 1999 May 31
File under Integrated Circuits, IC06
1999 Sep 24
INTEGRATED CIRCUITS
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
1999 Sep 24
2
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74AHC132; 74AHCT132
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V;
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
Inputs accepts voltages higher than
V
CC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
-
40 to +85 and +125
C.
DESCRIPTION
The 74AHC/AHCT132 are
high-speed Si-gate CMOS devices
and are pin compatible with Low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT132 contain four
2-input NAND gates which accept
standard input signals. They are
capable of transforming slowly
changing input signals into sharply
defined, jitter free output signals.
The gate switches at different points
for positive and negative-going
signals. The difference between the
positive voltage V
T+
and the negative
V
T
-
is defined as the hysteresis
voltage V
H
.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level; L = LOW voltage level.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
3.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
INPUTS
OUTPUT
nA
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
nA to nY
C
L
= 15 pF;
V
CC
= 5 V
3.3
3.5
ns
C
I
input capacitance
V
I
= V
CC
or GND
3.0
3.0
pF
C
O
output capacitance
4.0
4.0
pF
C
PD
power dissipation
capacitance
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
11
14
pF
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PACKAGES
PINS
PACKAGE
MATERIAL
CODE
74AHC132D
74AHC132D
14
SO
plastic
SOT108-1
74AHC132PW
74AHC132PW DH
14
TSSOP
plastic
SOT402-1
74AHCT132D
74AHCT132D
14
SO
plastic
SOT108-1
74AHCT132PW
74AHCT132PW DH
14
TSSOP
plastic
SOT402-1
1999 Sep 24
3
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74AHC132; 74AHCT132
PINNING
PIN
SYMBOL
DESCRIPTION
1, 4, 9 and 12
1A to 4A
data inputs
2, 5, 10 and 13
1B to 4B
data inputs
3, 6, 8 and 11
1Y to 4Y
data outputs
7
GND
ground (0 V)
14
V
CC
DC supply voltage
Fig.1 Pin configuration.
handbook, halfpage
MNA406
132
1
2
3
4
5
6
7
8
14
13
12
11
10
9
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
VCC
Fig.2 Logic symbol.
MNA407
handbook, halfpage
1A
1Y
1
3
1B
2
2A
2Y
4
6
2B
5
3A
3Y
9
8
3B
10
4A
4Y
12
11
4B
13
1999 Sep 24
4
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74AHC132; 74AHCT132
Fig.3 IEC logic symbol.
handbook, halfpage
2
3
&
1
5
6
&
4
10
8
&
9
MNA408
13
11
&
12
Fig.4 Logic diagram (one Schmitt trigger).
MNA409
handbook, halfpage
A
Y
B
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70
C the value of P
D
derates linearly with 8 mW/K.
For TSSOP packages: above 60
C the value of P
D
derates linearly with 5.5 mW/K.
SYMBOL
PARAMETER
CONDITIONS
74AHC
74AHCT
UNIT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
V
CC
DC supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
V
I
input voltage
0
-
5.5
0
-
5.5
V
V
O
output voltage
0
-
V
CC
0
-
V
CC
V
T
amb
operating ambient temperature
range
see DC and AC
characteristics per
device
-
40
+25
+85
-
40
+25
+85
C
-
40
+25
+125
-
40
+25
+125
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX. UNIT
V
CC
DC voltage
-
0.5
+7.0
V
V
I
input voltage range
-
0.5
+7.0
V
I
IK
DC input diode current
V
I
<
-
0.5 V; note 1
-
-
20
mA
I
OK
DC output diode current
V
O
<
-
0.5 V or V
O
> V
CC
+ 0.5 V; note 1
-
20
mA
I
O
DC output source or sink current
-
0.5 V < V
O
< V
CC
+ 0.5 V
-
25
mA
I
CC
DC V
CC
or GND current
-
75
mA
T
stg
storage temperature range
-
65
+150
C
P
D
power dissipation per package
for temperature range:
-
40 to +125
C; note 2
-
500
mW
1999 Sep 24
5
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74AHC132; 74AHCT132
DC CHARACTERISTICS
Type 74AHC132
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
C)
UNIT
OTHER
V
CC
(V)
25
-
40 to +85
-
40 to +125
MIN.
TYP.
MAX. MIN. MAX. MIN. MAX.
V
T+
positive going
threshold
3.0
-
-
2.2
-
2.2
-
2.2
V
4.5
-
-
3.15
-
3.15
-
3.15
5.5
-
-
3.85
-
3.85
-
3.85
V
T
-
negative going
threshold
3.0
0.9
-
-
0.9
-
0.9
-
V
4.5
1.35
-
-
1.35
-
1.35
-
5.5
1.65
-
-
1.65
-
1.65
-
V
H
hysteresis
(V
T+
-
V
T
-
)
3.0
0.3
-
1.2
0.3
1.2
0.25
1.2
V
4.5
0.4
-
1.4
0.4
1.4
0.35
1.4
5.5
0.5
-
1.6
0.5
1.6
0.45
1.6
V
OH
HIGH-level output
voltage; all
outputs
V
I
= V
IH
or V
IL
;
I
O
=
-
50
A
2.0
1.9
2.0
-
1.9
-
1.9
-
V
3.0
2.9
3.0
-
2.9
-
2.9
-
4.5
4.4
4.5
-
4.4
-
4.4
-
HIGH-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
=
-
4.0 mA
3.0
2.58
-
-
2.48
-
2.40
-
V
V
I
= V
IH
or V
IL
;
I
O
=
-
8.0 mA
4.5
3.94
-
-
3.8
-
3.7
-
V
OL
LOW-level output
voltage; all
outputs
V
I
= V
IH
or V
IL
;
I
O
= 50
A
2.0
-
0
0.1
-
0.1
-
0.1
V
3.0
-
0
0.1
-
0.1
-
0.1
4.5
-
0
0.1
-
0.1
-
0.1
LOW-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
= 4 mA
3.0
-
-
0.36
-
0.44
-
0.55
V
V
I
= V
IH
or V
IL
;
I
O
= 8 mA
4.5
-
-
0.36
-
0.44
-
0.55
I
I
input leakage
current
V
I
= V
CC
or GND
5.5
-
-
0.1
-
1.0
-
2.0
A
I
CC
quiescent supply
current
V
I
= V
CC
or GND;
I
O
= 0
5.5
-
-
2.0
-
20
-
40
A
C
I
input capacitance
-
3
10
-
10
-
10
pF