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Электронный компонент: 74AHC138D

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DATA SHEET
Product specification
Supersedes data of 1999 Mar 31
File under Integrated Circuits, IC06
1999 Sep 27
INTEGRATED CIRCUITS
74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer;
inverting
1999 Sep 27
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74AHC138;
74AHCT138
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Multiple input enable for easy
expansion
Ideal for memory chip select
decoding
Inputs accept voltages higher than
V
CC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
-
40 to +85 and +125
C.
DESCRIPTION
The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT138 decoders accept three binary weighted address inputs
(A
0
, A
1
and A
2
) and when enabled, provide 8 mutually exclusive active LOW
outputs (Y
0
to Y
7
).
The `138' features three enable inputs: two active LOW (E
1
and E
2
) and one
active HIGH (E
3
). Every output will be HIGH unless E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel expansion of the `138' to a
1-of-32 (5 to 32 lines) decoder with just four `138' ICs and one inverter.
The `138' can be used as an eight output demultiplexer by using one of the
active LOW enable inputs as the data input and the remaining enable inputs as
strobes. Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
The `138' is identical to the `238' but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
3.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay A
n
to Y
n
C
L
= 15 pF; V
CC
= 5 V
4.4
4.4
ns
propagation delay E
3
to Y
n
; E
n
to Y
n
C
L
= 15 pF; V
CC
= 5 V
4.2
4.3
ns
C
I
input capacitance
V
I
= V
CC
or GND
3.0
3.0
pF
C
O
output capacitance
4.0
4.0
pF
C
PD
power dissipation capacitance
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
18
23
pF
1999 Sep 27
3
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74AHC138;
74AHCT138
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don't care.
ORDERING INFORMATION
PINNING
INPUT
OUTPUT
E
1
E
2
E
3
A
0
A
1
A
2
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
H
X
X
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
L
X
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
H
H
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PACKAGES
PINS
PACKAGE
MATERIAL
CODE
74AHC138D
74AHC138D
16
SO
plastic
SOT109-1
74AHC138PW
74AHC138PW DH
16
TSSOP
plastic
SOT403-1
74AHCT138D
74AHCT138D
16
SO
plastic
SOT109-1
74AHCT138PW
74AHCT138PW DH
16
TSSOP
plastic
SOT403-1
PIN
SYMBOL
DESCRIPTION
1, 2 and 3
A
0
, A
1
and A
2
address inputs
4 and 5
E
1
and E
2
enable inputs (active LOW)
6
E
3
enable input (active HIGH)
7, 9, 10 11, 12, 13, 14 and 15
Y
7
to Y
0
outputs (active LOW)
8
GND
ground (0 V)
16
V
CC
DC supply voltage
1999 Sep 27
4
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74AHC138;
74AHCT138
Fig.1 Pin configuration.
handbook, halfpage
138
MNA369
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
A2
E1
E2
E3
Y7
GND
Y6
Y5
Y4
Y3
Y2
Y1
Y0
VCC
Fig.2 Logic symbol.
handbook, halfpage
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
7
9
10
11
12
13
14
15
A0
A1
A2
3
2
1
6
5
4
E2
E1
E3
MNA370
Fig.3 IEC logic symbol.
handbook, halfpage
MNA371
7
9
10
11
12
13
14
&
X/Y
15
7
EN
6
5
4
3
2
1
0
6
5
4
3
2
1
1
4
2
7
9
10
11
12
13
14
&
DX
(a)
(b)
15
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
2
G
0
7
Fig.4 Functional diagram.
handbook, halfpage
MNA372
ENABLE
EXITING
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
7
9
10
11
12
13
14
15
A0
A1
A2
3-to-8
DECODER
3
2
1
6
5
4
E2
E1
E3
Fig.4 Functional diagram.
1999 Sep 27
5
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74AHC138;
74AHCT138
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70
C the value of P
D
derates linearly with 8 mW/K.
For TSSOP packages: above 60
C the value of P
D
derates linearly with 5.5 mW/K.
SYMBOL
PARAMETER
CONDITIONS
74AHC
74AHCT
UNIT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
V
CC
DC supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
V
I
input voltage
0
-
5.5
0
-
5.5
V
V
O
output voltage
0
-
V
CC
0
-
V
CC
V
T
amb
operating ambient temperature
range
see DC and AC
characteristics per
device
-
40
+25
+85
-
40
+25
+85
C
-
40
+25
+125
-
40
+25
+125
C
t
r
,t
f
(
t/
f) input rise and fall rates
V
CC
= 3.3 V
0.3 V
-
-
100
-
-
-
ns/V
V
CC
= 5 V
0.5 V
-
-
20
-
-
20
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX. UNIT
V
CC
DC supply voltage
-
0.5
+7.0
V
V
I
input voltage range
-
0.5
+7.0
V
I
IK
DC input diode current
V
I
<
-
0.5 V; note 1
-
-
20
mA
I
OK
DC output diode current
V
O
<
-
0.5 V or V
O
> V
CC
+ 0.5 V; note 1
-
20
mA
I
O
DC output source or sink current
-
0.5 V < V
O
< V
CC
+ 0.5 V
-
25
mA
I
CC
DC V
CC
or GND current
-
75
mA
T
stg
storage temperature range
-
65
+150
C
P
D
power dissipation per package
for temperature range:
-
40 to +125
C; note 2
-
500
mW