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Электронный компонент: 74AHC257PW

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DATA SHEET
Product specification
File under Integrated Circuits, IC06
2000 Apr 03
INTEGRATED CIRCUITS
74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
2000 Apr 03
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74AHC257;
74AHCT257
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Non-inverting data path
Inputs accept voltages higher than V
CC
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
-
40 to +85
C and
-
40 to +125
C.
DESCRIPTION
The 74AHC/AHCT257 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT257 has four identical 2-input
multiplexers with 3-state outputs, which select 4 bits of
data from two sources and are controlled by a common
data select input (S).
The data inputs from source 0 (1I
0
to 4I
0
) are selected
when input S is LOW and the data inputs from source 1
(1I
1
to 4I
1
) are selected when S is HIGH. Data appears at
the outputs (1Y to 4Y) in true (non-inverting) form from the
selected inputs.
The 74AHC/AHCT257 is the logic implementation of a
4-pole 2-position switch, where the position of the switch is
determined by the logic levels applied to S. The outputs
are forced to a high impedance OFF-state when OE is
HIGH.
If OE is LOW then the logic equations for the outputs are:
1Y = 1I
1
S + 1I
0
S;
2Y = 2I
1
S + 2I
0
S;
3Y = 3I
1
S + 3I
0
S;
4Y = 4I
1
S + 4I
0
S.
The `257' is identical to the `258' but has non-inverting
(true) outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
3.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
nl
0
, nI
1
to nY
C
L
= 15 pF; V
CC
= 5 V
2.9
3.7
ns
S to nY
C
L
= 15 pF; V
CC
= 5 V
3.5
5.1
ns
C
I
input capacitance
V
I
= V
CC
or GND
3.0
3.0
pF
C
O
output capacitance
4.0
4.0
pF
C
PD
power dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz; notes 1 and 2
4 outputs switching via input S
45
51
pF
1 output switching via input I
15
15
pF
2000 Apr 03
3
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74AHC257;
74AHCT257
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don't care;
Z = high impedance OFF-state.
ORDERING INFORMATION
PINNING
INPUT
OUTPUT
OE
S
nI
0
nI
1
nY
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
X
L
L
L
H
X
H
TYPE NUMBER
PACKAGES
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74AHC257D
-
40 to +125
C
16
SO
plastic
SOT109-1
74AHC257PW
16
TSSOP
plastic
SOT403-1
74AHCT257D
16
SO
plastic
SOT109-1
74AHCT257PW
16
TSSOP
plastic
SOT403-1
PIN
SYMBOL
DESCRIPTION
1
S
common data select input
2, 5, 11 and 14
1I
0
to 4I
0
data inputs from source 0
3, 6, 10 and 13
1I
1
to 4I
1
data inputs from source 1
4, 7, 9 and 12
1Y to 4Y
multiplexer outputs
8
GND
ground (0 V)
15
OE
output enable input (active LOW)
16
V
CC
DC supply voltage
2000 Apr 03
4
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74AHC257;
74AHCT257
handbook, halfpage
257
MNA536
1
2
3
4
5
6
7
8
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
VCC
OE
4I0
4I1
4Y
3I0
3I1
3Y
16
15
14
13
12
11
10
9
Fig.1 Pin configuration.
handbook, halfpage
MNA537
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1
S
1Y
2Y
3Y
4Y
1
15
12
9
7
4
13
14
10
11
6
5
3
2
OE
Fig.2 Logic symbol.
MNA538
handbook, halfpage
12
9
7
15
1
G1
EN
MUX
1
1
4
13
14
10
11
6
5
3
2
Fig.3 IEC logic symbol.
handbook, halfpage
MNA540
3-STATE
MULTIPLEXER
OUTPUTS
SELECTOR
2Y
3Y
4Y 12
9
7
2I0
2I1
3I0
3I1
4I0
4I1
S
OE
13
15
1
14
10
11
6
5
1Y
4
1I0
1I1
3
2
Fig.4 Functional diagram.
2000 Apr 03
5
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74AHC257;
74AHCT257
handbook, full pagewidth
MNA539
2Y
3Y
4Y
2I0
2I1
3I0
3I1
4I0
4I1
S
OE
1Y
1I0
1I1
Fig.5 Logic diagram.