DATA SHEET
Product specification
File under Integrated Circuits, IC06
1999 Sep 01
INTEGRATED CIRCUITS
74AHC273; 74AHCT273
Octal D-type flip-flop with reset;
positive-edge trigger
1999 Sep 01
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
FEATURES
Ideal buffer for MOS microcontroller or memory
Common clock and master reset
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt trigger actions
Inputs accepts voltages higher than V
CC
See `377' for clock enable version
See `373' for transparent latch version
See `374' for 3-state version
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
-
40 to +85
C and
-
40 to +125
C.
DESCRIPTION
The 74AHC/AHCT273 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
C; t
r
= t
f
3.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
CP to Q
n
4.2
4.0
ns
MR to Q
n
3.7
3.9
ns
f
max
maximum clock frequency
C
L
= 15 pF; V
CC
= 5 V
120
120
MHz
C
I
input capacitance
V
I
= V
CC
or GND
3.0
3.0
pF
C
O
output capacitance
4.0
4.0
pF
C
PD
power dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
14.0
18.0
pF
1999 Sep 01
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don't care;
= LOW-to-HIGH transition.
ORDERING INFORMATION
PINNING
OPERATING MODES
INPUTS
OUTPUTS
MR
CP
D
n
Q
n
reset (clear)
L
X
X
L
load `1'
H
h
L
load `0'
H
l
L
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PACKAGES
PINS
PACKAGE
MATERIAL
CODE
74AHC273D
74AHC273D
20
SO
plastic
SOT163-1
74AHC273PW
74AHC273PW DH
20
TSSOP
plastic
SOT360-1
74AHCT273D
74AHCT273D
20
SO
plastic
SOT163-1
74AHCT273PW
7AHCT273PW DH
20
TSSOP
plastic
SOT360-1
PIN
SYMBOL
DESCRIPTION
1
MR
master reset input (active LOW)
2, 5, 6, 9, 12, 15, 16 and 19 Q
0
to Q
7
flip-flop outputs
3, 4, 7, 8, 13, 14, 17 and 18 D
0
to D
7
data inputs
10
GND
ground (0 V)
11
CP
clock input (LOW-to-HIGH; edge-triggered)
20
V
CC
DC supply voltage
1999 Sep 01
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
Fig.1 Pin configuration.
handbook, halfpage
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q5
D5
Q6
D4
Q4
CP
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
273
MNA459
Fig.2 Logic symbol.
handbook, halfpage
MNA460
D0
D1
D2
D3
D4
D5
D6
D7
MR
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
Fig.3 IEC logic symbol.
handbook, halfpage
MNA461
19
16
15
12
9
6
5
11
C1
1
R
1D
2
18
17
14
13
8
7
4
3
Fig.4 Functional diagram.
handbook, halfpage
MNA462
FF1
to
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 19
16
15
12
9
6
5
2
D0
D1
D2
D3
D4
D5
D6
D7
CP
MR
18
11
1
17
14
13
8
7
4
3
1999 Sep 01
5
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
Fig.5 Logic diagram.
handbook, full pagewidth
MNA463
Q0
D0
D
FF1
Q
CP
RD
CP
MR
Q1
D1
D
FF2
Q
CP
RD
Q2
D2
D
FF3
Q
CP
RD
Q3
D3
D
FF4
Q
CP
RD
Q4
D4
D
FF5
Q
CP
RD
Q5
D5
D
FF6
Q
CP
RD
Q6
D6
D
FF7
Q
CP
RD
Q7
D7
D
FF8
Q
CP
RD
1999 Sep 01
6
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO package: above 70
C the value of P
D
derates linearly with 8 mW/K.
For TSSOP package: above 60
C the value of P
D
derates linearly with 5.5 mW/K.
SYMBOL
PARAMETER
CONDITIONS
74AHC
74AHCT
UNIT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
V
CC
DC supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
V
I
input voltage
0
-
5.5
0
-
5.5
V
V
O
output voltage
0
-
V
CC
0
-
V
CC
V
T
amb
operating ambient
temperature
see DC and AC
characteristics per device
-
40
+25
+85
-
40
+25
+85
C
-
40
+25
+125
-
40
+25
+125
C
t
r
,t
f
(
t/
f)
input rise and fall ratio V
CC
= 3.3
0.3 V
-
-
100
-
-
-
ns/V
V
CC
= 5
0.5 V
-
-
20
-
-
20
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX. UNIT
V
CC
DC supply voltage
-
0.5
+7.0
V
V
I
input voltage
-
0.5
+7.0
V
I
IK
DC input diode current
V
I
<
-
0.5 V; note 1
-
-
20
mA
I
OK
DC output diode current
V
O
<
-
0.5 V or V
O
> V
CC
+ 0.5 V; note 1
-
20
mA
I
O
DC output source or sink current
-
0.5 V < V
O
< V
CC
+ 0.5 V
-
25
mA
I
CC
DC V
CC
or GND current
-
75
mA
T
stg
storage temperature
-
65
+150
C
P
D
power dissipation per package
for temperature range:
-
40 to +125
C;
note 2
-
500
mW
1999 Sep 01
7
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
DC CHARACTERISTICS
Family 74AHC
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
C)
UNIT
OTHER
V
CC
(V)
25
-
40 to +85
-
40 to +125
MIN.
TYP.
MAX. MIN. MAX. MIN. MAX.
V
IH
HIGH-level input
voltage
2.0
1.5
-
-
1.5
-
1.5
-
V
3.0
2.1
-
-
2.1
-
2.1
-
5.5
3.85
-
-
3.85
-
3.85
-
V
IL
LOW-level input
voltage
2.0
-
-
0.5
-
0.5
-
0.5
V
3.0
-
-
0.9
-
0.9
-
0.9
5.5
-
-
1.65
-
1.65
-
1.65
V
OH
HIGH-level output
voltage; all outputs
V
I
= V
IH
or V
IL
;
I
O
=
-
50
A
2.0
1.9
2.0
-
1.9
-
1.9
-
V
3.0
2.9
3.0
-
2.9
-
2.9
-
4.5
4.4
4.5
-
4.4
-
4.4
-
HIGH-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
=
-
4.0 mA
3.0
2.58
-
-
2.48
-
2.40
-
V
V
I
= V
IH
or V
IL
;
I
O
=
-
8.0 mA
4.5
3.94
-
-
3.8
-
3.70
-
V
OL
LOW-level output
voltage; all outputs
V
I
= V
IH
or V
IL
;
I
O
= 50
A
2.0
-
0
0.1
-
0.1
-
0.1
V
3.0
-
0
0.1
-
0.1
-
0.1
4.5
-
0
0.1
-
0.1
-
0.1
LOW-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
= 4.0 mA
3.0
-
-
0.36
-
0.44
-
0.55
V
V
I
= V
IH
or V
IL
;
I
O
= 8.0 mA
4.5
-
-
0.36
-
0.44
-
0.55
I
I
input leakage
current
V
I
= V
CC
or GND
5.5
-
-
0.1
-
1.0
-
2.0
A
I
OZ
3-state output
OFF current
V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND
5.5
-
-
0.25
-
2.5
-
10.0
A
I
CC
quiescent supply
current
V
I
= V
CC
or GND;
I
O
= 0
5.5
-
-
4.0
-
40
-
80
A
C
I
input capacitance
-
-
3
10
-
10
-
10
pF
1999 Sep 01
8
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
Family 74AHCT
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
C)
UNIT
OTHER
V
CC
(V)
25
-
40 to +85
-
40 to +125
MIN.
TYP. MAX. MIN. MAX. MIN. MAX.
V
IH
HIGH-level input
voltage
4.5 to 5.5
2.0
-
-
2.0
-
2.0
-
V
V
IL
LOW-level input
voltage
4.5 to 5.5
-
-
0.8
-
0.8
-
0.8
V
V
OH
HIGH-level
output voltage;
all outputs
V
I
= V
IH
or V
IL
;
I
O
=
-
50
A
4.5
4.4
4.5
-
4.4
-
4.4
-
V
HIGH-level
output voltage
V
I
= V
IH
or V
IL
;
I
O
=
-
8.0 mA
4.5
3.94
-
-
3.8
-
3.70
-
V
V
OL
LOW-level output
voltage; all
outputs
V
I
= V
IH
or V
IL
;
I
O
= 50
A
4.5
-
0
0.1
-
0.1
-
0.1
V
LOW-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
= 8.0 mA
4.5
-
-
0.36
-
0.44
-
0.55
V
I
I
input leakage
current
V
I
= V
IH
or V
IL
5.5
-
-
0.1
-
1.0
-
2.0
A
I
OZ
3-state output
OFF current
V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND
per input pin;
other inputs at
V
CC
or GND;
I
O
= 0
5.5
-
-
0.25
-
2.5
-
10.0
A
I
CC
quiescent supply
current
V
I
= V
CC
or GND;
I
O
= 0
5.5
-
-
4.0
-
40
-
80
A
I
CC
additional
quiescent supply
current per input
pin
V
I
= V
CC
-
2.1 V;
other inputs at
V
CC
or GND;
I
O
= 0
4.5 to 5.5
-
-
1.35
-
1.5
-
1.5
mA
C
I
input
capacitance
-
-
3
10
-
10
-
10
pF
1999 Sep 01
9
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
AC CHARACTERISTICS
Type 74AHC273
Ground = 0 V; t
r
= t
f
3.0 ns.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
C)
UNIT
WAVEFORMS
C
L
25
-
40 to +85
-
40 to +125
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
V
CC
= 3.0 to 3.6 V; note 1
t
PHL
/t
PLH
propagation delay
CP to Q
n
see Figs 6 and 9
15 pF
-
6.0
13.6
1.0
16.0
1.0
17.0
ns
t
PHL
propagation delay
MR to Q
n
see Figs 7 and 9
-
5.1
13.6
1.0
16.0
1.0
17.0
ns
f
max
maximum clock
pulse frequency
75
120
-
65
-
65
-
ns
t
PHL
/t
PLH
propagation delay
CP to Q
n
see Figs 6 and 9
50 pF
-
8.6
17.1
1.0
19.5
1.0
21.5
ns
t
PHL
propagation delay
MR to Q
n
see Figs 7 and 9
-
7.3
17.1
1.0
19.5
1.0
21.5
ns
t
W
clock pulse width
HIGH or LOW
see Figs 6 and 9
5.0
-
-
6.5
-
6.5
-
ns
master reset
pulse width LOW
see Figs 7 and 9
5.0
-
-
6.0
-
6.0
-
ns
t
rem
removal time
MR to CP
2.5
-
-
2.5
-
2.5
-
ns
t
su
set-up time
D
n
to CP
see Figs 8 and 9
3.0
-
-
3.0
-
3.0
-
ns
t
h
hold time
D
n
to CP
1.0
-
-
1.0
-
1.0
-
ns
f
max
maximum clock
pulse frequency
50
75
-
45
-
45
-
ns
1999 Sep 01
10
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
Notes
1. Typical values at V
CC
= 3.3 V.
2. Typical values at V
CC
= 5.0 V.
V
CC
= 4.5 to 5.5 V; note 2
t
PHL
/t
PLH
propagation delay
CP to Q
n
see Figs 6 and 9
15 pF
-
4.2
9.0
1.0
10.5
1.0
11.5
ns
t
PHL
propagation delay
MR to Q
n
see Figs 7 and 9
-
3.7
8.5
1.0
10.0
1.0
11.0
ns
f
max
maximum clock
pulse frequency
120
165
-
100
-
100
-
ns
t
PHL
/t
PLH
propagation delay
CP to Q
n
see Figs 6 and 9
50 pF
-
6.0
11.0
1.0
12.5
1.0
14.0
ns
t
PHL
propagation delay
MR to Q
n
see Figs 7 and 9
-
5.3
10.5
1.0
12.0
1.0
13.5
ns
t
W
clock pulse width
HIGH or LOW
see Figs 6 and 9
5.0
-
-
5.0
-
5.0
-
ns
master reset
pulse width LOW
see Figs 7 and 9
5.0
-
-
5.0
-
5.0
-
ns
t
rem
removal time
MR to CP
2.0
-
-
2.0
-
2.0
-
ns
t
su
set-up time
D
n
to CP
see Figs 8 and 9
3.0
-
-
3.0
-
3.0
-
ns
t
h
hold time
D
n
to CP
1.0
-
-
1.0
-
1.0
-
ns
f
max
maximum clock
pulse frequency
80
110
-
70
-
70
-
ns
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
C)
UNIT
WAVEFORMS
C
L
25
-
40 to +85
-
40 to +125
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
1999 Sep 01
11
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
Type 74AHCT273
Ground = 0 V; t
r
= t
f
3.0 ns.
Note
1. Typical values at V
CC
= 5.0 V.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
C)
UNIT
WAVEFORMS
C
L
25
-
40 to +85
-
40 to +125
MIN.
TYP.
MAX. MIN.
MAX. MIN.
MAX.
V
CC
= 4.5 to 5.5 V; note 1
t
PHL
/t
PLH
propagation delay
CP to Q
n
see Figs 6 and 9
15 pF
-
4.0
7.5
1.0
8.8
1.0
9.5
ns
t
PHL
propagation delay
MR to Q
n
see Figs 7 and 9
-
3.9
10.0
1.0
11.6
1.0
12.5
ns
f
max
maximum clock
pulse frequency
75
120
-
65
-
65
-
ns
t
PHL
/t
PLH
propagation delay
CP to Q
n
see Figs 6 and 9
50 pF
-
5.8
9.2
1.0
10.5
1.0
11.5
ns
t
PHL
propagation delay
MR to Q
n
see Figs 7 and 9
-
5.6
11.0
1.0
12.6
1.0
14.0
ns
t
W
clock pulse width
HIGH or LOW
see Figs 6 and 9
5.0
-
-
6.5
-
6.5
-
ns
master reset
pulse width LOW
see Figs 7 and 9
5.0
-
-
6.0
-
6.0
-
ns
t
rem
removal time
MR to CP
2.5
-
-
2.5
-
2.5
-
ns
t
su
setup time
D
n
to CP
see Figs 8 and 9
3.0
-
-
3.0
-
3.0
-
ns
t
h
hold time
D
n
to CP
1.0
-
-
1.0
-
1.0
-
ns
f
max
maximum clock
pulse frequency
50
75
-
45
-
45
-
ns
1999 Sep 01
12
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
AC WAVEFORMS
Fig.6
The clock (CP) to output (Q
n
) propagation delays, the clock pulse width output transition times and the
maximum clock pulse frequency.
FAMILY
V
I
INPUT
REQUIREMENTS
V
M
INPUT
V
M
OUTPUT
AHC
GND to V
CC
50% V
CC
50% V
CC
AHCT
GND to 3.0 V
1.5 V
50% V
CC
handbook, full pagewidth
MNA200
tPHL
tPLH
tW
1/fmax
VM
(1)
VM
(1)
CP INPUT
Qn OUTPUT
GND
VI
Fig.7
The master reset (MR) pulse width, the master reset to output (Q
n
) propagation delays and master reset
to clock (CP) removal time.
FAMILY
V
I
INPUT
REQUIREMENTS
V
M
INPUT
V
M
OUTPUT
AHC
GND to V
CC
50% V
CC
50% V
CC
AHCT
GND to 3.0 V
1.5 V
50% V
CC
handbook, full pagewidth
MNA464
MR INPUT
CP INPUT
Qn OUTPUT
tPLH
tW
trem
VM
(1)
VI
VI
GND
VI
GND
GND
VM
(1)
VM
(1)
1999 Sep 01
13
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
handbook, full pagewidth
MNA202
GND
GND
th
th
tsu
tsu
VM
(1)
VM
(1)
VM
(1)
VI
VI
Qn OUTPUT
CP INPUT
Dn INPUT
Fig.8 The data set-up and hold times for the data input (D
n
).
The shaded areas indicate when the input is permitted to change for predicable output performance.
FAMILY
V
I
INPUT
REQUIREMENTS
V
M
INPUT
V
M
OUTPUT
AHC
GND to V
CC
50% V
CC
50% V
CC
AHCT
GND to 3.0 V
1.5 V
50% V
CC
Fig.9 Load circuitry for switching times.
handbook, full pagewidth
open
GND
VCC
VCC
VI
VO
MNA183
D.U.T.
CL
RT
1000
PULSE
GENERATOR
S1
TEST
S
1
t
PLH
/t
PHL
open
t
PLZ
/t
PZL
V
CC
t
PHZ
/t
PZH
GND
Definitions for test circuit.
C
L
= load capacitance including jig and probe capacitance (See Chapter "AC characteristics").
R
L
= load resistance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
1999 Sep 01
14
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
PACKAGE OUTLINES
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
2.65
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.1
1.0
0.9
0.4
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.1
0.4
SOT163-1
10
20
w
M
b
p
detail X
Z
e
11
1
D
y
0.25
075E04
MS-013AC
pin 1 index
0.10
0.012
0.004
0.096
0.089
0.019
0.014
0.013
0.009
0.51
0.49
0.30
0.29
0.050
1.4
0.055
0.419
0.394
0.043
0.039
0.035
0.016
0.01
0.25
0.01
0.004
0.043
0.016
0.01
0
5
10 mm
scale
X
A
A
1
A
2
H
E
L
p
Q
E
c
L
v
M
A
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
95-01-24
97-05-22
1999 Sep 01
15
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
UNIT
A
1
A
2
A
3
b
p
c
D
(1)
E
(2)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.5
0.2
8
0
o
o
0.13
0.1
0.2
1.0
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1
MO-153AC
93-06-16
95-02-04
w
M
b
p
D
Z
e
0.25
1
10
20
11
pin 1 index
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0
2.5
5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
A
max.
1.10
1999 Sep 01
16
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"Data Handbook IC26; Integrated Circuit Packages"
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250
C. The top-surface temperature of the
packages should preferable be kept below 230
C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
For packages with leads on two sides and a pitch (e):
larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
For packages with leads on four sides, the footprint must
be placed at a 45
angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300
C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320
C.
1999 Sep 01
17
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45
angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PACKAGE
SOLDERING METHOD
WAVE
REFLOW
(1)
BGA, SQFP
not suitable
suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not suitable
(2)
suitable
PLCC
(3)
, SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended
(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended
(5)
suitable
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1999 Sep 01
18
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
NOTES
1999 Sep 01
19
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
NOTES
Philips Electronics N.V.
SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
1999
67
Philips Semiconductors a worldwide company
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Printed in The Netherlands
245002/01/pp
20
Date of release:
1999 Sep 01
Document order number:
9397 750 06158
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