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Электронный компонент: 74AHCT374

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DATA SHEET
Product specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC06
1999 Sep 28
INTEGRATED CIRCUITS
74AHC374; 74AHCT374
Octal D-type flip-flop; positive
edge-trigger; 3-state
1999 Sep 28
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374;
74AHCT374
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Inputs accepts voltages higher than
V
CC
Common 3-state output enable
input
I
CC
category: MSI
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
-
40 to +85 and +125
C.
DESCRIPTION
The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT374 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation
of the OE input does not affect the state of the flip-flops.
The `374' is functionally identical to the `534', but has non-inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
3.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay;
CP to Q
n
C
L
= 15 pF; V
CC
= 5 V
3.5
5.0
ns
f
max
maximum clock frequency
C
L
= 15 pF; V
CC
= 5 V
50
-
MHz
C
I
input capacitance
V
I
= V
CC
or GND
3.0
3.0
pF
C
O
output capacitance
4.0
4.0
pF
C
PD
power dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
10
12
pF
1999 Sep 28
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374;
74AHCT374
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
X = don't care;
Z = high-impedance OFF-state;
= LOW-to-HIGH CP transition.
ORDERING INFORMATION
PINNING
OPERATING MODES
INPUTS
INTERNAL
FLIP-FLOPS
OUTPUTS
OE
CP
D
n
Q
0
to Q
7
Load and read register
L
I
L
L
L
h
H
H
Load register and
disable outputs
H
l
L
Z
H
h
H
Z
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PACKAGES
PINS
PACKAGE
MATERIAL
CODE
74AHC374D
74AHC374D
20
SO
plastic
SOT163-1
74AHC374PW
74AHC374PW DH
20
TSSOP
plastic
SOT360-1
74AHCT374D
74AHCT374D
20
SO
plastic
SOT163-1
74AHCT374PW
7AHCT374PW DH
20
TSSOP
plastic
SOT360-1
PIN
SYMBOL
DESCRIPTION
1
OE
3-state output enable input (active LOW)
2, 5, 6, 9, 12, 15,
16 and 19
Q
0
to Q
7
3-state flip-flop outputs
3, 4, 7, 8, 13, 14,
17 and 18
D
0
to D
7
data inputs
10
GND
ground (0 V)
11
CP
clock input (LOW-to-HIGH, edge triggered)
20
V
CC
DC supply voltage
1999 Sep 28
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374;
74AHCT374
Fig.1 Pin configuration.
handbook, halfpage
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q5
D5
Q6
D4
Q4
CP
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
374
MNA194
Fig.2 Logic symbol.
handbook, halfpage
MNA195
D0
D1
D2
D3
D4
D5
D6
D7
OE
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
Fig.3 IEC logic symbol.
handbook, halfpage
MNA196
19
16
15
12
9
6
5
11
C1
1
EN
1D
2
18
17
14
13
8
7
4
3
Fig.4 Functional diagram.
handbook, halfpage
MNA197
3-STATE
OUTPUTS
FF1
to
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 19
16
15
12
9
6
5
2
D0
D1
D2
D3
D4
D5
D6
D7
CP
OE
18
11
1
17
14
13
8
7
4
3
1999 Sep 28
5
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374;
74AHCT374
MNA198
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
D
FF1
Q
CP
CP
D
FF2
Q
CP
D
FF3
Q
CP
D
FF4
Q
CP
D
FF5
Q
CP
D
FF6
Q
CP
D
FF7
Q
CP
D
FF8
Q
CP
OE
Q5
D5
Q6
D6
Q7
D7
Fig.5 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
74AHC
74AHCT
UNIT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
V
CC
DC supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
V
I
input voltage
0
-
5.5
0
-
5.5
V
V
O
output voltage
0
-
V
CC
0
-
V
CC
V
T
amb
operating ambient temperature
range
see DC and AC
characteristics per
device
-
40
+25
+85
-
40
+25
+85
C
-
40
+25
+125
-
40
+25
+125
C
t
r
,t
f
(
t/
f) input rise and fall rates
V
CC
= 3.3 V
0.3 V
-
-
100
-
-
-
ns/V
V
CC
= 5 V
0.5 V
-
-
20
-
-
20