Philips
Semiconductors
74ALVCH16501
18-bit universal bus transceiver (3-State)
Product specification
Supersedes data of 1998 Aug 31
IC24 Data Handbook
1998 Sep 29
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74ALVCH16501
18-bit universal bus transceiver (3-State)
2
1998 Sep 29
8532091 20106
FEATURES
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
24 mA at 3.0 V
Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched or clocked mode.
All inputs have bushold circuitry
Output drive capability 50
transmission lines @ 85
C
3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16501 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
AB
and OE
BA
), latch enable (LE
AB
and LE
BA
), and clock
(CP
AB
and CP
BA
) inputs. For A-to-B data flow, the device operates
in the transparent mode when LE
AB
is High. When LE
AB
is Low, the
A data is latched if CP
AB
is held at a High or Low logic level. If LE
AB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP
AB
. When OE
AB
is High, the outputs are
active. When OE
AB
is Low, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
. The output enables are complimentary (OE
AB
is active
High, and OE
BA
is active Low).
To ensure the high impedance state during power up or power
down, OE
BA
should be tied to V
CC
through a pullup resistor and
OE
AB
should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
= t
f
= 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An, Bn to Bn, An
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.8
3.0
ns
C
I/O
Input/output capacitance
8.0
pF
C
I
Input capacitance
4.0
pF
C
PD
Power dissipation capacitance per
V
I
= GND to V
CC
1
Outputs enabled
21
pF
C
PD
latch
V
I
= GND to V
CC
1
Outputs disabled
3
F
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
S
(C
L
V
CC
2
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
V
CC
2
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
DWG NUMBER
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ALVCH16501 DGG
SOT364-1
Philips Semiconductors
Product specification
74ALVCH16501
18-bit universal bus transceiver (3-State)
1998 Sep 29
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
OE
AB
LE
AB
A0
GND
A1
A2
V
CC
A4
A5
GND
A6
A7
A8
A9
A3
A10
A11
GND
A12
A13
B13
B12
GND
B11
B10
B9
B8
B7
B6
GND
B5
B4
B3
V
CC
B2
B1
GND
A0
CP
AB
GND
21
22
23
24
33
34
35
36
A14
V
CC
A15
A16
B16
B15
V
CC
B14
25
26
27
28
29
30
31
32
GND
A17
OE
BA
LE
BA
GND
CP
BA
B17
GND
SW00089
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
OE
AB
Output enable A-to-B
2
LE
AB
Latch enable A-to-B
3, 5, 6, 8, 9,
10, 12, 13, 14,
15, 16, 17, 19,
20, 21, 23, 24,
26
A0 to A17
Data inputs/outputs
4, 11, 18, 25,
29, 32, 39, 46,
53, 56
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
27
OE
BA
Output enable B-to-A
28
LE
BA
Latch enable B-to-A
30
CP
BA
Clock input B-to-A
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
B0 to B17
Data inputs/outputs
55
CP
AB
Clock input A-to-B
LOGIC SYMBOL (IEEE/IEC)
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D
1
1
4
1
6D
1
56
2
27
30
28
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
SW00088
OE
AB
CP
AB
LE
AB
OE
BA
CP
BA
LE
BA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
Philips Semiconductors
Product specification
74ALVCH16501
18-bit universal bus transceiver (3-State)
1998 Sep 29
4
LOGIC SYMBOL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
OE
AB
LE
AB
CP
AB
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
OE
BA
LE
BA
CP
BA
3
5
6
8
10
12
13
14
15
16
17
19
20
21
23
24
26
1
2
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
27
28
30
9
SW00087
BUS HOLD CIRCUIT
To internal circuit
V
CC
Data Input
SW00044
LOGIC DIAGRAM (one section)
C1
1D
C1
1D
C1
1D
C1
1D
18 IDENTICAL CHANNELS
A1
OE
BA
LE
AB
CP
AB
LE
BA
CP
BA
OE
AB
B1
SW00091
Philips Semiconductors
Product specification
74ALVCH16501
18-bit universal bus transceiver (3-State)
1998 Sep 29
5
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
OEAB
LEAB
CPAB
An
Bn
L
X
X
X
Z
Disabled
H
H
X
H
H
Transparent
H
H
X
L
L
Trans arent
H
X
h
H
Latch data & display
H
X
I
L
Latch data & dis lay
H
L
h
H
Clock data & display
H
L
I
L
Clock data & dis lay
H
L
H or L
X
H
Hold data & display
H
L
H or L
X
L
Hold data & dis lay
NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level
h
= High voltage level one set-up time prior to the Enable or Clock transition
L
= Low voltage level
I
= Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don't care
Z = High Impedance "off" state
= High-to-Low Enable or Clock transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
2.3
2.7
V
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
3.0
3.6
V
V
I
DC Input voltage range
0
V
CC
V
V
O
DC output voltage range
0
V
CC
V
T
amb
Operating free-air temperature range
40
+85
C
t
r
, t
f
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
0
0
20
10
ns/V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +4.6
V
I
IK
DC input diode current
V
I
t
0
50
mA
V
I
DC input voltage
For control pins
1
0.5 to +4.6
V
V
I
DC in ut voltage
For data inputs
1
0.5 to V
CC
+0.5
V
I
OK
DC output diode current
V
O
u
V
CC
or V
O
t
0
"
50
mA
V
O
DC output voltage
Note 1
0.5 to V
CC
+0.5
V
I
O
DC output source or sink current
V
O
= 0 to V
CC
"
50
mA
I
GND
, I
CC
DC V
CC
or GND current
"
100
mA
T
stg
Storage temperature range
65 to +150
C
P
TOT
Power dissipation per package
plastic thin-medium-shrink (TSSOP)
For temperature range: 40 to +125
C
above +55
C derate linearly with 8 mW/K
600
mW
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
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