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Электронный компонент: 74ALVCH16601

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Philips
Semiconductors
74ALVCH16601
18-bit universal bus transceiver (3-State)
Product specification
Supersedes data of 1998 Aug 31
IC24 Data Handbook
1998 Sep 24
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74ALVCH16601
18-bit universal bus transceiver (3-State)
2
1998 Sep 24
853-2122 20076
FEATURES
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
Current drive
24 mA at 3.0 V
All inputs have bus hold circuitry
Output drive capability 50
transmission lines @ 85
C
DESCRIPTION
The 74ALVCH16601 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
AB
and OE
BA
), latch enable (LE
AB
and LE
BA
), and clock
(CP
AB
and CP
BA
) inputs. For A-to-B data flow, the device operates
in the transparent mode when LE
AB
is High. When LE
AB
is Low, the
A data is latched if CP
AB
is held at a High or Low logic level. If LE
AB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP
AB
. When OE
AB
is Low, the outputs are
active. When OE
AB
is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CE
BA
/CE
AB
).
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
.
To ensure the high impedance state during power up or power
down, OE
BA
and OE
AB
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
= t
f
= 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An, Bn to Bn, An
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
3.1
2.8
ns
C
I/O
Input/Output capacitance
8.0
pF
C
I
Input capacitance
4.0
pF
C
Power dissipation capacitance per latch
V = GND to V
CC
1
Outputs enabled
21
pF
C
PD
Power dissipation capacitance per latch
V
I
= GND to V
CC
1
Outputs disabled
3
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
m
W):
P
D
= C
PD
V
CC
2
f
i
+
S
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
V
CC
2
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
DWG NUMBER
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ALVCH16601 DGG
SOT364-1
Philips Semiconductors
Product specification
74ALVCH16601
18-bit universal bus transceiver (3-State)
1998 Sep 24
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
27
28
30
29
OE
AB
LE
AB
A0
GND
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A11
GND
A12
VCC
A10
A13
A14
A15
A16
A17
VCC
GND
OE
BA
LE
BA
CE
AB
CP
AB
B0
GND
B1
B2
B3
B4
B5
GND
B6
B7
B8
B9
B11
GND
B12
VCC
B10
B13
B14
B15
B16
B17
VCC
GND
CP
BA
CE
BA
SW00129
LOGIC SYMBOL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
OE
AB
LE
AB
CP
AB
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
OE
BA
LE
BA
CP
BA
3
5
6
8
10
12
13
14
15
16
17
19
20
21
23
24
26
1
2
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
27
28
30
9
SW00130
CE
AB
56
CE
BA
29
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
OE
AB
Output enable A-to-B
2
LE
AB
Latch enable A-to-B
3, 5, 6, 8, 9,
10, 12, 13, 14,
15, 16, 17, 19,
20, 21, 23, 24,
26
A0 to A17
Data inputs/outputs
4, 11, 18, 25,
32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
27
OE
BA
Output enable B-to-A
28
LE
BA
Latch enable B-to-A
29
CE
BA
Clock enable B-to-A
30
CP
BA
Clock input B-to-A
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
B0 to B17
Data inputs/outputs
55
CP
AB
Clock input A-to-B
56
CE
AB
Clock enable A-to-B
Philips Semiconductors
Product specification
74ALVCH16601
18-bit universal bus transceiver (3-State)
1998 Sep 24
4
LOGIC DIAGRAM (one section)
CE
C1
CP
1D
CE
C1
CP
1D
18 IDENTICAL CHANNELS
A1
B1
OE
BA
CE
BA
LE
BA
CP
BA
OE
AB
CE
AB
LE
AB
CP
AB
SW00132
FUNCTION TABLE
INPUTS
OUTPUTS
STATUS
CE
XX
OE
XX
LE
XX
CP
XX
DATA
OUTPUTS
STATUS
X
H
X
X
X
Z
Disabled
X
X
L
L
H
H
X
X
H
L
H
L
Transparent
H
L
L
X
X
NC
Hold
L
L
L
L
L
L
h
l
H
L
Clock + display
L
L
L
L
L
L
L
H
X
X
NC
Hold
XX
=
AB for A-to-B direction, BA for B-to-A direction
H
=
HIGH voltage level
L
=
LOW voltage level
h
=
HIGH state must be present one setup time before the LOW-to-HIGH transition of CP
XX
l
=
LOW state must be present one setup time before the LOW-to-HIGH transition of CP
XX
X
=
Don't care
=
LOW-to-HIGH level transition
NC
=
No change
Z
=
High impedance "off " state
Philips Semiconductors
Product specification
74ALVCH16601
18-bit universal bus transceiver (3-State)
1998 Sep 24
5
LOGIC SYMBOL (IEEE/IEC)
EN1
G2
2C3
C3
G2
EN4
3D
4
6D
56
55
1
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
SW00133
OE
AB
CP
AB
LE
AB
A0
A1
A2
A3
A4
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
G5
5C6
C6
G5
29
30
28
27
OE
BA
CP
BA
CE
BA
LE
BA
CE
AB
A5
24
26
33
31
A16
A17
B16
B17
1
BUSHOLD CIRCUIT
To internal circuit
V
CC
Data Input
SW00050