Philips Semiconductors
Product specification
74ALVT162823
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30
termination resistors (3-State)
2
1998 Aug 27
853-2114 19927
FEATURES
Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
5V I/O Compatible
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Live insertion/extraction permitted
Power-up 3-State
Power-up Reset
Output capability: +12mA/12mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Outputs include series resistance of 30
making external
termination resistors unnecessary
DESCRIPTION
The 74ALVT162823 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ALVT162823 has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop's Q output.
The 74ALVT162823 is designed with 30
series resistance in both
the pull-up and pull-down output structures. This design reduces line
noise in applications such as memory address drivers, clock drivers,
and bus receivers/transmitters.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
SYMBOL
PARAMETER
T
amb
= 25
C; GND = 0V
2.5V
3.3V
UNIT
t
PLH
t
PHL
Propagation delay
nCP to nQx
C
L
= 50pF
4.2
3.4
3.0
2.8
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
3
3
pF
C
OUT
Output capacitance
V
I/O
= 0V or 3.0V
9
9
pF
I
CCZ
Total supply current
Outputs disabled
40
70
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
40
C to +85
C
74ALVT162823 DL
AV162823 DL
SOT3711
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ALVT162823 DGG
AV162823 DGG
SOT3641
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2, 27
1OE, 2OE
Output enable input (active-Low)
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
1D0-1D8
2D0-2D8
Data inputs
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
1Q0-1Q8
2Q0-2Q8
Data outputs
56, 29
1CP, 2CP
Clock pulse input (active rising edge)
55, 30
1CE, 2CE
Clock enable input (active-Low)
1, 28
1MR, 2MR
Master reset input (active-Low)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74ALVT162823
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30
termination resistors (3-State)
1998 Aug 27
4
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
nOE
nMR
nCE
nCP
nDx
nQ0 nQ8
OPERATING MODE
L
L
X
X
X
L
Clear
L
H
L
h
H
Load and read data
L
H
L
l
L
Load and read data
L
H
H
X
NC
Hold
H
X
X
X
X
Z
High impedance
H = High voltage level
h
= High voltage level one set-up time prior to the Low-to-High clock transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don't care
Z = High impedance "off" state
= Low to High clock transition
= Not a Low-to-High clock transition
SCHEMATIC OF EACH OUTPUT
V
CC
V
CC
OUTPUT
27
27
SW00007
BUS HOLD CIRCUIT
To internal circuit
V
CC
Data Input
SW00044
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
-0.5 to +4.6
V
I
IK
DC input diode current
V
I
< 0
-50
mA
V
I
DC input voltage
3
-0.5 to +7.0
V
I
OK
DC output diode current
V
O
< 0
-50
mA
V
OUT
DC output voltage
3
Output in Off or High state
-0.5 to +7.0
V
I
O
DC output current
Output in Low state
128
mA
I
OUT
DC output current
Output in High state
-64
mA
T
stg
Storage temperature range
-65 to +150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Philips Semiconductors
Product specification
74ALVT162823
2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset
and enable with 30
termination resistors (3-State)
1998 Aug 27
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
2.5V RANGE LIMITS
3.3V RANGE LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
V
CC
DC supply voltage
2.3
2.7
3.0
3.6
V
V
I
Input voltage
0
5.5
0
5.5
V
V
IH
High-level input voltage
1.7
2.0
V
V
IL
Input voltage
0.7
0.8
V
I
OH
High-level output current
8
12
mA
I
OL
Low-level output current
12
12
mA
t/
v
Input transition rise or fall rate; Outputs enabled
10
10
ns/V
T
amb
Operating free-air temperature range
40
+85
40
+85
C
DC ELECTRICAL CHARACTERISTICS (3.3V
"
0.3V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
C to +85
C
UNIT
MIN
TYP
1
MAX
V
IK
Input clamp voltage
V
CC
= 3.0V; I
IK
= 18mA
0.85
1.2
V
V
OH
High-level output voltage
V
CC
= 3.0V; I
OH
= 12mA
2.0
2.3
V
V
OL
Low-level output voltage
V
CC
= 3 0V; I
OL
= 12mA
0 5
0 8
V
V
OL
Low-level out ut voltage
V
CC
= 3.0V; I
OL
= 12mA
0.5
0.8
V
V
RST
Power-up output low voltage
6
V
CC
= 3.6V; I
O
= 1mA; V
I
= V
CC
or GND
0.55
V
V
CC
= 3.6V; V
I
= V
CC
or GND
Control pins
0.1
1
A
V
CC
= 0 or 3.6V; V
I
= 5.5V
Control ins
0.1
10
I
I
Input leakage current
V
CC
= 3.6V; V
I
= 5.5V
0.1
10
A
V
CC
= 3.6V; V
I
= V
CC
Data pins
4
0.5
1
V
CC
= 3.6V; V
I
= 0
0.1
-5
I
OFF
Off current
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
0.1
100
A
Bus Hold current
V
CC
= 3V; V
I
= 0.8V
75
130
I
HOLD
Bus Hold current
D inputs
7
V
CC
= 3V; V
I
= 2.0V
75
140
A
D inputs
7
V
CC
= 0V to 3.6V; V
CC
= 3.6V
500
I
EX
Current into an output in the
High state when V
O
> V
CC
V
O
= 5.5V; V
CC
= 3.0V
10
125
A
I
PU/PD
Power up/down 3-State output
current
3
V
CC
1.2V; V
O
= 0.5V to V
CC
; V
I
= GND or V
CC
OE/OE = Don't care
1
100
A
I
OZH
3-State output High current
V
CC
= 3.6V; V
O
= 3.0V; V
I
= V
IL
or V
IH
0.5
5
A
I
OZL
3-State output Low current
V
CC
= 3.6V; V
O
= 0.5V; V
I
= V
IL
or V
IH
0.5
5
A
I
CCH
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
0.05
0.1
I
CCL
Quiescent supply current
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
3.9
5.5
mA
I
CCZ
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
5
0.06
0.1
I
CC
Additional supply current per
input pin
2
V
CC
= 3V to 3.6V; One input at V
CC
0.6V,
Other inputs at V
CC
or GND
0.04
0.4
mA
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
0.3V a
transition time of 100
sec is permitted. This parameter is valid for T
amb
= 25
C only.
4. Unused pins at V
CC
or GND.
5. I
CCZ
is measured with outputs pulled up to V
CC
or pulled down to ground.
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
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