DATA SHEET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jul 08
INTEGRATED CIRCUITS
74HC/HCT123
Dual retriggerable monostable
multivibrator with reset
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
1998 Jul 08
2
Philips Semiconductors
Product specification
Dual retriggerable monostable
multivibrator with reset
74HC/HCT123
FEATURES
DC triggered from active HIGH or
active LOW inputs
Retriggerable for very long pulses
up to 100% duty factor
Direct reset terminates output
pulse
Schmitt-trigger action on all inputs
except for the reset input
Output capability: standard (except
for nR
EXT
/C
EXT
)
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT123 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT123 are dual
retriggerable monostable
multivibrators with output pulse width
control by three methods. The basic
pulse time is programmed by
selection of an external resistor
(R
EXT
) and capacitor (C
EXT
). The
external resistor and capacitor are
normally connected as shown in
Fig.6.
Once triggered, the basic output
pulse width may be extended by
retriggering the gated active
LOW-going edge input (nA) or the
active HIGH-going edge input (nB).
By repeating this process, the output
pulse period (nQ = HIGH, nQ = LOW)
can be made as long as desired.
Alternatively an output delay can be
terminated at any time by a
LOW-going edge on input nR
D
, which
also inhibits the triggering.
An internal connection from nR
D
to
the input gates makes it possible to
trigger the circuit by a positive-going
signal at input nR
D
as shown in the
function table. Figures 7 and 8
illustrate pulse control by retriggering
and early reset. The basic output
pulse width is essentially determined
by the values of the external timing
components R
EXT
and C
EXT
. For
pulse widths, when C
EXT
<
10 000 pF,
see Fig.9.
When C
EXT
>
10 000 pF, the typical
output pulse width is defined as:
t
W
= 0.45
R
EXT
C
EXT
(typ.),
where:
t
W
= pulse width in ns;
R
EXT
= external resistor in k
;
C
EXT
= external capacitor in pF.
Schmitt-trigger action in the nA and
nB inputs, makes the circuit highly
tolerant to slower input rise and fall
times.
The `123' is identical to the `423' but
can be triggered via the reset input.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) + 0.75
C
EXT
V
CC
2
f
o
+
D
16
V
CC
where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
D = duty factor in %
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
C
EXT
= timing capacitance in pF
(C
L
V
CC
2
f
o
) sum of outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF;
V
CC
= 5 V;
R
EXT
= 5 k
;
C
EXT
= 0 pF
nA, nB to nQ, nQ
26
26
ns
nR
D
to nQ, nQ
20
23
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation
capacitance per
monostable
notes 1 and 2
54
56
pF
1998 Jul 08
3
Philips Semiconductors
Product specification
Dual retriggerable monostable
multivibrator with reset
74HC/HCT123
ORDERING INFORMATION
PIN DESCRIPTION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC123N;
74HCT123N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HC123D;
74HCT123D
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC123DB;
74HCT123DB
SSOP16
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
74HC123PW;
74HCT123PW
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 9
1A, 2A
trigger inputs (negative-edge triggered)
2, 10
1B, 2B
trigger inputs (positive-edge triggered)
3, 11
1R
D
, 2R
D
direct reset LOW and trigger action at positive edge
4, 12
1Q, 2Q
outputs (active LOW)
7
2R
EXT
/C
EXT
external resistor/capacitor connection
8
GND
ground (0 V)
13, 5
1Q, 2Q
outputs (active HIGH)
14, 6
1C
EXT
, 2C
EXT
external capacitor connection
15
1R
EXT
/C
EXT
external resistor/capacitor connection
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
4
Philips Semiconductors
Product specification
Dual retriggerable monostable
multivibrator with reset
74HC/HCT123
Fig.4 Functional diagram.
FUNCTION TABLE
Note
1. If the monostable was triggered
before this condition was
established, the pulse will
continue as programmed.
INPUTS
OUTPUTS
nR
D
nA
nB
nQ
nQ
L
X
X
L
H
X
H
X
L
(1)
H
(1)
X
X
L
L
(1)
H
(1)
H
L
H
H
L
H
H
= HIGH voltage level
L
= LOW voltage level
X
= don't care
= LOW-to-HIGH transition
= HIGH-to-LOW transition
= one HIGH level output pulse
= one LOW level output pulse
Fig.5 Logic diagram.
(1) For minimum noise generation,
it is recommended to ground pins 6 (2C
EXT
)
and 14 (1C
EXT
) externally to pin 8 (GND).
1998 Jul 08
5
Philips Semiconductors
Product specification
Dual retriggerable monostable
multivibrator with reset
74HC/HCT123
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard (except for nR
EXT
/C
EXT
)
I
CC
category: MSI
Fig.6 Timing component connections.
PDF 
ZIP