DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT153
Dual 4-input multiplexer
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Dual 4-input multiplexer
74HC/HCT153
FEATURES
Non-inverting output
Separate enable for each output
Common select inputs
See `253" for 3-state version
Permits multiplexing from n lines to
1 line
Enable line provided for cascading
(n lines to 1 line)
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT153 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT153 have two
identical 4-input multiplexers which
select two bits of data from up to four
sources selected by common data
select inputs (S
0
, S
1
). The two 4-input
multiplexer circuits have individual
active LOW output enable inputs (1E,
2E) which can be used to strobe the
outputs independently. The outputs
(1Y, 2Y) are forced LOW when the
corresponding output enable inputs
are HIGH.
The "153" is the logic implementation
of a 2-pole, 4-position switch, where
the position of the switch is
determined by the logic levels applied
to S
0
and S
1
.
The logic equations for the outputs
are:
1Y = 1E.(1I
0
.S
1
.S
0
+1I
1
.S
1
.S
0
+
+1I
2
.S
1
.S
0
+1I
3
.S
1
.S
0
)
2Y = 2E.(2I
0
.S
1
.S
0
+2I
1
.S
1
.S
0
+
+2I
2
.S
1
.S
0
+2I
3
.S
1
.S
0
)
The "153" can be used to move data
to a common output bus from a group
of registers. The state of the select
inputs would determine the particular
register from which the data came. An
alternative application is a function
generator. The device can generate
two functions or three variables. This
is useful for implementing highly
irregular random logic.
The "153" is similar to the "253" but
has standard outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
1I
n
, 2I
n
to nY
14
16
ns
S
n
to nY
15
17
ns
nE to nY
10
11
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per multiplexer notes 1 and 2
30
30
pF
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
(C
L
V
CC
2
f
o
) = sum of outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic
Package Information"
.
December 1990
3
Philips Semiconductors
Product specification
Dual 4-input multiplexer
74HC/HCT153
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 15
1E, 2E
output enable inputs (active LOW)
14, 2
S
0
, S
1
common data select inputs
6, 5, 4, 3
1I
0
to 1I
3
data inputs from source 1
7
1Y
multiplexer output from source 1
8
GND
ground (0 V)
9
2Y
multiplexer output from source 2
10, 11, 12, 13
2I
0
to 2I
3
data inputs from source 2
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
December 1990
5
Philips Semiconductors
Product specification
Dual 4-input multiplexer
74HC/HCT153
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25
-
40 to+85
-
40 to+125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
1I
n
to nY;
2I
n
to nY
47
17
14
145
29
25
180
36
31
220
44
38
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
S
n
to nY
50
18
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
nE to nY
33
12
10
100
20
17
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 6 and 7
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