DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT165
8-bit parallel-in/serial-out shift
register
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
FEATURES
Asynchronous 8-bit parallel load
Synchronous serial input
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q
7
and
Q
7
) available from the last stage. When the parallel load
(PL) input is LOW, parallel data from the D
0
to
D
7
inputs are loaded into the register asynchronously.
When PL is HIGH, data enters the register serially at the
D
s
input and shifts one place to the right
(Q
0
Q
1
Q
2
, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter
expansion by tying the Q
7
output to the D
S
input of the
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
APPLICATIONS
Parallel-to-serial data conversion
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
CP to Q
7,
Q
7
PL to Q
7,
Q
7
D
7
to Q
7,
Q
7
C
L
= 15 pF; V
CC
= 5 V
16
15
11
14
17
11
ns
ns
ns
f
max
maximum clock frequency
56
48
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per
package
notes 1 and 2
35
35
pF
December 1990
3
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
PL
asynchronous parallel load input (active LOW)
7
Q
7
complementary output from the last stage
9
Q
7
serial output from the last stage
2
CP
clock input (LOW-to-HIGH edge-triggered)
8
GND
ground (0 V)
10
D
s
serial data input
11, 12, 13, 14, 3, 4, 5, 6
D
0
to D
7
parallel data inputs
15
CE
clock enable input (active LOW)
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH clock transition
X = don't care
= LOW-to-HIGH clock transition
OPERATING MODES
INPUTS
Q
n
REGISTERS
OUTPUTS
PL
CE
CP
D
S
D
0
-D
7
Q
0
Q
1
-Q
6
Q
7
Q
7
parallel load
L
L
X
X
X
X
X
X
L
H
L
H
L - L
H - H
L
H
H
L
serial shift
H
H
L
L
l
h
X
X
L
H
q
0
-q
5
q
0
-q
5
q
6
q
6
q
6
q
6
hold "do nothing"
H
H
X
X
X
q
0
q
1
-q
6
q
7
q
7
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT165
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
CE, CP to Q
7
, Q
7
52
19
15
165
33
28
205
41
35
250
50
43
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
PL to Q
7
, Q
7
50
18
14
165
33
28
205
41
35
250
50
43
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
D
7
to Q
7
, Q
7
36
13
10
120
24
20
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
W
parallel load pulse
width; LOW
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
rem
removal time
PL to CP, CE
100
20
17
22
8
6
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.6
t
su
set-up time
D
s
to CP, CE
80
16
14
11
4
3
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
su
set-up time
CE to CP;
CP to CE
80
16
14
17
6
5
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
t
su
set-up time
D
n
to PL
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
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