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Электронный компонент: 74HC240N

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DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT240
Octal buffer/line driver; 3-state;
inverting
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state;
inverting
74HC/HCT240
FEATURES
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT240 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT240 are octal inverting buffer/line drivers
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH on nOE
causes the outputs to assume a high impedance
OFF-state. The "240" is identical to the "244" but has
inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
1A
n
to 1Y
n
;
2A
n
to 2Y
n
C
L
= 15 pF; V
CC
= 5 V
9
9
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per buffer
notes 1 and 2
30
30
pF
December 1990
3
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state; inverting
74HC/HCT240
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
1OE
output enable input (active LOW)
2, 4, 6, 8
1A
0
to 1A
3
data inputs
3, 5, 7, 9
2Y
0
to 2Y
3
bus outputs
10
GND
ground (0 V)
17, 15, 13, 11
2A
0
to 2A
3
data inputs
18, 16, 14, 12
1Y
0
to 1Y
3
bus outputs
19
2OE
output enable input (active LOW)
20
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state; inverting
74HC/HCT240
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don't care
Z = high impedance OFF-state
INPUTS
OUTPUT
nOE
nA
n
nY
n
L
L
H
L
H
X
H
L
Z
December 1990
5
Philips Semiconductors
Product specification
Octal buffer/line driver; 3-state; inverting
74HC/HCT240
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max.
min.
max.
min. max.
t
PHL
/ t
PLH
propagation delay
1A
n
to 1Y
n
;
2A
n
to 2Y
n
30
11
9
100
20
17
125
25
21
150
30
26
ns
2.0
4.5
6.0
Fig.5
t
PZH
/ t
PZL
3-state output enable time
1OE to 1Y
n
;
2OE to 2Y
n
39
14
11
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.6
t
PHZ
/ t
PLZ
3-state output disable time
1OE to 1Y
n
;
2OE to 2Y
n
41
15
12
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.5