Document Outline
- FEATURES
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- FUNCTION TABLE
- DC CHARACTERISTICS
- AC CHARACTERISTICS
- AC WAVEFORMS
- PACKAGE OUTLINES
- SOT38-1
- SOT109-1
- SOT338-1
- SOT403-1
- SOLDERING
- DEFINITIONS
DATA SHEET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Sep 30
INTEGRATED CIRCUITS
74HC/HCT257
Quad 2-input multiplexer; 3-state
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
1998 Sep 30
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74HC/HCT257
FEATURES
Non-inverting data path
3-state outputs interface directly with system bus
Output capability: bus driver
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT257 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT257 have four identical 2-input multiplexers
with 3-state outputs, which select 4 bits of data from two
sources and are controlled by a common data select
input (S).
The data inputs from source 0 (1I
0
to 4I
0
) are selected
when input S is LOW and the data inputs from source 1
(1I
1
to 4I
1
) are selected when S is HIGH. Data appears at
the outputs (1Y to 4Y) in true (non-inverting) form from the
selected inputs.
The "257" is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S. The outputs
are forced to a high impedance OFF-state when OE is
HIGH.
The logic equations for the outputs are:
1Y = OE.(1I
1
.S
+
1I
0
.S)
2Y = OE.(2I
1
.S
+
2I
0
.S)
3Y = OE.(3I
1
.S
+
3I
0
.S)
4Y = OE.(4I
1
.S
+
4I
0
.S)
The "257" is identical to the "258" but has non-inverting
(true) outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
nI
0
, nI
1
to nY
11
13
ns
S to nY
14
17
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per multiplexer
notes 1 and 2
45
45
pF
1998 Sep 30
3
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74HC/HCT257
ORDERING INFORMATION
PIN DESCRIPTION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC257N;
74HCT257N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HC257D;
74HCT257D
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC257DB;
74HCT257DB
SSOP16
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
74HC257PW;
74HCT257PW
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
PIN NO.
SYMBOL
NAME AND FUNCTION
1
S
common data select input
2, 5, 11, 14
1I
0
to 4I
0
data inputs from source 0
3, 6, 10, 13
1I
1
to 4I
1
data inputs from source 1
4, 7, 9, 12
1Y to 4Y
3-state multiplexer outputs
8
GND
ground (0 V)
15
OE
3-state output enable input (active LOW)
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
fpage
GND
VCC
MLB311
S
OE
1Y
2Y
4Y
3Y
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
257
1I0
1I1
2I0
2I1
4I0
4I1
3I0
3I1
Fig.2 Logic symbol.
fpage
MGA835
S
OE
1Y
2Y
3Y
4Y
2
3
5
6
11
10
14
13
15
1
4
7
9
12
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
Fig.3 IEC logic symbol.
1998 Sep 30
4
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74HC/HCT257
Fig.4 Functional diagram.
MGR280
S
1
1I0
2
1Y
4
1I1
3
SELECTOR
3-STATE MULTIPLEXER OUTPUTS
2I0
5
2Y
7
2I1
6
3I0
11
3Y
12
3I1
10
4I0
14
4Y
9
4I1
13
OE
15
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don't care
Z = high impedance OFF-state
INPUTS
OUTPUT
OE
S
nI
0
nI
1
nY
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
X
L
L
L
H
X
H
Fig.5 Logic diagram.
1998 Sep 30
5
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74HC/HCT257
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ. max. min. max.
min.
max.
t
PHL
/ t
PLH
propagation delay
nI
0
to nY;
nI
1
to nY
36
110
140
165
ns
2.0
Fig.6
13
22
28
33
4.5
10
19
24
28
6.0
t
PHL
/ t
PLH
propagation delay
S to nY
47
150
190
225
ns
2.0
Fig.6
17
30
38
45
4.5
14
26
33
38
6.0
t
PZH
/ t
PZL
3-state output enable time
OE to nY
33
150
190
225
ns
2.0
Fig.7
12
30
38
45
4.5
10
26
33
38
6.0
t
PHZ
/ t
PLZ
3-state output disable time
OE to nY
41
150
190
225
ns
2.0
Fig.7
15
30
38
45
4.5
12
26
33
38
6.0
t
THL
/ t
TLH
output transition time
14
60
75
90
ns
2.0
Fig.6
5
12
15
18
4.5
4
10
13
15
6.0
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