Philips
Semiconductors
74LV373
Octal D-type transparent latch (3-State)
Product specification
Supersedes data of 1997 March 04
IC24 Data Handbook
1998 Jun 10
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LV373
Octal D-type transparent latch (3-State)
2
1998 Jun 10
8531934 19545
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce) < 0.8V at V
CC
= 3.3V,
T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot) > 2V at V
CC
= 3.3V,
T
amb
= 25
C
Common 3-State output enable input
Output capability: bus driver
I
CC
category: MSI
DESCRIPTION
The 74LV373 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT373.
The 74LV373 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
The `373' consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The `373' is functionally identical to the `573', but the `573' has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
= t
f
v
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
D
n
to Q
n
LE to Q
n
C
L
= 15pF
V
CC
= 3.3V
10
12
ns
C
I
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per latch
Notes 1, 2
22
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
x f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
40
C to +125
C
74LV373 N
74LV373 N
SOT146-1
20-Pin Plastic SO
40
C to +125
C
74LV373 D
74LV373 D
SOT163-1
20-Pin Plastic SSOP Type II
40
C to +125
C
74LV373 DB
74LV373 DB
SOT339-1
20-Pin Plastic TSSOP Type I
40
C to +125
C
74LV373 PW
74LV373PW DH
SOT360-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enabled input (active LOW)
2, 5, 6, 9, 12,
15, 16, 19
Q
0
Q
7
3-State latch outputs
3, 4, 7, 8, 13,
14, 17, 18
D
0
D
7
Data inputs
10
GND
Ground (0V)
11
LE
Latch enable input (active HIGH)
20
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74LV373
Octal D-type transparent latch (3-State)
1998 Jun 10
3
PIN CONFIGURATION
SV00657
Q
0
Q
1
Q
2
Q
3
GND
Q
4
Q
5
Q
6
Q
7
D
0
D
1
D
2
D
3
V
CC
D
4
D
5
D
6
D
7
LE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
LOGIC SYMBOL
SV00658
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
2
5
6
9
12
15
16
19
11
3
4
7
8
13
14
17
18
1
OE
LOGIC SYMBOL (IEEE/IEC)
SV00659
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
C1
EN1
1D
11
1
FUNCTIONAL DIAGRAM
SV00660
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
1
LATCH
1 to 8
3STATE
OUTPUTS
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
11
OE
LOGIC DIAGRAM
LATCH
1
D
Q
LE LE
Q0
D
0
LATCH
2
D
Q
LE LE
Q1
D
1
LATCH
3
D
Q
LE LE
Q2
D
2
LATCH
4
D
Q
LE LE
Q3
D
3
LATCH
5
D
Q
LE LE
Q4
D
4
LATCH
6
D
Q
LE LE
Q5
D
5
LATCH
7
D
Q
LE LE
Q6
D
6
LATCH
8
D
Q
LE LE
Q7
D
7
LE
OE
SV00661
Philips Semiconductors
Product specification
74LV373
Octal D-type transparent latch (3-State)
1998 Jun 10
4
FUNCTION TABLE
OPERATING MODES
INPUTS
INTERNAL
OUTPUTS
OPERATING MODES
OE
LE
Dn
LATCHES
Q
0
to Q
7
Enable and read register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
Latch and read register
L
L
L
L
I
h
L
H
L
H
Latch register and disable outputs
H
H
L
L
I
h
L
H
Z
Z
H = HIGH voltage level
h
= HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L
= LOW voltage level
I
= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X = Don't care
Z = High impedance OFF-state
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNIT
V
CC
DC supply voltage
See Note1
1.0
3.3
5.5
V
V
I
Input voltage
0
V
CC
V
V
O
Output voltage
0
V
CC
V
T
amb
Operating ambient temperature range in free
air
See DC and AC
characteristics
40
40
+85
+125
C
t
r
, t
f
Input rise and fall times
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
500
200
100
50
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0.5 or V
I
> V
CC
+ 0.5V
20
mA
I
OK
DC output diode current
V
O
< 0.5 or V
O
> V
CC
+ 0.5V
50
mA
I
O
DC output source or sink current
bus driver outputs
0.5V < V
O
< V
CC
+ 0.5V
35
mA
I
GND
,
I
CC
DC V
CC
or GND current for types with
bus driver outputs
70
mA
T
stg
Storage temperature range
65 to +150
C
Power dissipation per package
for temperature range: 40 to +125
C
P
t t
plastic DIL
above +70
C derate linearly with 12mW/K
750
mW
P
tot
plastic mini-pack (SO)
above +70
C derate linearly with 8 mW/K
500
mW
plastic shrink mini-pack (SSOP and TSSOP)
above +60
C derate linearly with 5.5 mW/K
400
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors
Product specification
74LV373
Octal D-type transparent latch (3-State)
1998 Jun 10
5
DC CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
-40
C to +85
C
-40
C to +125
C
UNIT
MIN
TYP
1
MAX
MIN
MAX
V
CC
= 1.2V
0.9
0.9
V
HIGH level Input
V
CC
= 2.0V
1.4
1.4
V
V
IH
voltage
V
CC
= 2.7 to 3.6V
2.0
2.0
V
V
CC
= 4.5 to 5.5V
0.7*V
CC
0.7*V
CC
V
CC
= 1.2V
0.3
0.3
V
LOW level Input
V
CC
= 2.0V
0.6
0.6
V
V
IL
voltage
V
CC
= 2.7 to 3.6V
0.8
0.8
V
V
CC
= 4.5 to 5.5
0.3*V
CC
0.3*V
CC
V
CC
= 1.2V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.2
HIGH l
l
t
t
V
CC
= 2.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.8
2.0
1.8
HIGH level output
voltage; all outputs
V
CC
= 2.7V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.5
2.7
2.5
V
OH
voltage all out uts
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.8
3.0
2.8
V
V
OH
V
CC
= 4.5V; V
I
= V
IH
or V
IL;
I
O
= 100
A
4.3
4.5
4.3
V
HIGH level output
voltage; BUS driver
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 8mA
2.40
2.82
2.20
voltage; BUS driver
outputs
V
CC
= 4.5V; V
I
= V
IH
or V
IL;
I
O
= 16mA
3.60
4.20
3.50
V
CC
= 1.2V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
LOW l
l
t
t
V
CC
= 2.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
LOW level output
voltage; all outputs
V
CC
= 2.7V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
OL
voltage all out uts
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
V
OL
V
CC
= 4.5V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
LOW level output
voltage; BUS driver
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 8mA
0.20
0.40
0.50
voltage; BUS driver
outputs
V
CC
= 4.5V; V
I
= V
IH
or V
IL;
I
O
= 16mA
0.35
0.55
0.65
I
I
Input leakage
current
V
CC
= 5.5V; V
I
= V
CC
or GND
1.0
1.0
A
I
OZ
3-State output
OFF-state current
V
CC
= 5.5V; V
I
= V
IH
or V
IL;
V
O
= V
CC
or GND
5
10
A
I
CC
Quiescent supply
current; MSI
V
CC
= 5.5V; V
I
= V
CC
or GND; I
O
= 0
20.0
160
A
I
CC
Additional
quiescent supply
current per input
V
CC
= 2.7V to 3.6V; V
I
= V
CC
0.6V
500
850
A
NOTE:
1. All typical values are measured at T
amb
= 25
C.
PDF 
ZIP