Philips Semiconductors
Product specification
74ALVCH16821
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2
1998 May 29
853-2066 19467
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
Current drive
24 mA at 3.0 V
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
All data inputs have bus hold
Output drive capability 50
transmission lines @ 85
C
DESCRIPTION
The 74ALVCH16821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop's Q output.
When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16821 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
= t
f
2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nCP to nQ
n
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.6
2.5
ns
C
I
Input capacitance
5.0
pF
C
Power dissipation capacitance per buffer
V = GND to V
CC
1
Outputs enabled
33
pF
C
PD
Power dissipation capacitance per buffer
V
I
= GND to V
CC
1
Outputs disabled
17
pF
F
max
Maximum clock frequency
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
250
350
MHz
NOTE:
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
m
W):
P
D
= C
PD
V
CC
2
f
i
+
S
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
V
CC
2
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
40
C to +85
C
74ALVCH16821 DL
ACH16821 DL
SOT371-1
56-Pin Plastic TSSOP Type II
40
C to +85
C
74ALVCH16821 DGG
ACH16821 DGG
SOT364-1
Philips Semiconductors
Product specification
74ALVCH16821
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
1998 May 29
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
55, 54, 52, 51, 49,
48, 47, 45, 44, 43
1D0 - 1D9
Data inputs
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
2D0 - 2D9
Data in uts
2, 3, 5, 6, 8,
9, 10, 12, 13, 14
1Q0 - 1Q9
Data outputs
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
2Q0 - 2Q9
Data out uts
1, 28
1OE, 2OE
Output enable inputs
(active-Low)
56, 29
1CP, 2CP
Clock pulse inputs
(active rising edge)
4, 11, 18, 25,
32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply
voltage
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
GND
V
CC
GND
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
V
CC
2Q6
2Q7
GND
2Q8
2Q9
2OE
1CP
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
V
CC
2D6
2D7
GND
2D8
2D9
2CP
SH00001
FUNCTION TABLE
INPUTS
OUTPUT
nOE
CP
Dx
Q
L
L
L
L
H
H
L
}
X
Q0
H
X
X
Z
H = HIGH voltage level
L
= LOW voltage level
X = Don't care
Z = High impedance OFF state
= LOW to HIGH clock transition
}
= Not a LOW-to-HIGH clock transition
LOGIC SYMBOL
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1D8
1D9
1Q8
1Q9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2D8
2D9
2Q8
2Q9
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
1CP
1OE
2CP
2OE
56
1
29
28
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
SH00127
Philips Semiconductors
Product specification
74ALVCH16821
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
1998 May 29
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
2.3
2.7
V
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
3.0
3.6
V
V
I
DC Input voltage range
0
V
CC
V
V
O
DC output voltage range
0
V
CC
V
T
amb
Operating free-air temperature range
40
+85
C
t
r
, t
f
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
0
0
20
10
ns/V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +4.6
V
I
IK
DC input diode current
V
I
t
0
50
mA
V
I
DC input voltage
For control pins
1
0.5 to +4.6
V
V
I
DC in ut voltage
For data inputs
1
0.5 to V
CC
+0.5
V
I
OK
DC output diode current
V
O
u
V
CC
or V
O
t
0
"
50
mA
V
O
DC output voltage
Note 1
0.5 to V
CC
+0.5
V
I
O
DC output source or sink current
V
O
= 0 to V
CC
"
50
mA
I
GND
, I
CC
DC V
CC
or GND current
"
100
mA
T
stg
Storage temperature range
65 to +150
C
P
TOT
Power dissipation per package
plastic medium-shrink (SSOP)
plastic thin-medium-shrink (TSSOP)
For temperature range: 40 to +125
C
above +55
C derate linearly with 11.3 mW/K
above +55
C derate linearly with 8 mW/K
850
600
mW
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
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