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Электронный компонент: BSP100

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Philips Semiconductors
Product specification
N-channel enhancement mode
BSP100
TrenchMOS
TM
transistor
FEATURES
SYMBOL
QUICK REFERENCE DATA
'Trench' technology
V
DSS
= 30 V
Low on-state resistance
Fast switching
I
D
= 6 A
High thermal cycling performance
Low thermal resistance
R
DS(ON)
100 m
(V
GS
= 10 V)
R
DS(ON)
200 m
(V
GS
= 4.5 V)
GENERAL DESCRIPTION
PINNING
SOT223
N-channel
enhancement
mode
PIN
DESCRIPTION
field-effect transistor in a plastic
envelope
using
'trench'
1
gate
technology.
2
drain
Applications:-
 Motor and relay drivers
3
source
d.c. to d.c. converters
Logic level translator
4
drain (tab)
The BSP100 is supplied in the
SOT223
surface
mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 150C
-
30
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 150C; R
GS
= 20 k
-
30
V
V
GS
Gate-source voltage
-
20
V
I
D
Continuous drain current
T
sp
= 25 C
-
6
1
A
T
sp
= 100 C
-
4.4
A
T
amb
= 25 C
-
3.2
A
I
DM
Pulsed drain current
T
sp
= 25 C
-
24
A
P
D
Total power dissipation
T
sp
= 25 C
-
8.3
W
T
j
, T
stg
Operating junction and
- 65
150
C
storage temperature
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-sp
Thermal resistance junction to
surface mounted, FR4
12
15
K/W
solder point
board
R
th j-amb
Thermal resistance junction to
surface mounted, FR4
70
-
K/W
ambient
board
d
g
s
4
1
2
3
1 Continuous current rating limited by package
February 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
BSP100
TrenchMOS
TM
transistor
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
E
AS
Non-repetitive avalanche
Unclamped inductive load, I
AS
= 6 A;
-
23
mJ
energy
t
p
= 0.2 ms; T
j
prior to avalanche = 25C;
V
DD
15 V; R
GS
= 50
; V
GS
= 10 V
I
AS
Non-repetitive avalanche
-
6
A
current
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 10
A;
30
-
-
V
voltage
T
j
= -55C
27
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1
2
2.8
V
T
j
= 150C
0.4
-
-
V
T
j
= -55C
-
3.2
V
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 2.2 A
-
80
100
m
resistance
V
GS
= 4.5 V; I
D
= 1 A
-
120
200
m
V
GS
= 10 V; I
D
= 2.2 A; T
j
= 150C
-
-
170
m
g
fs
Forward transconductance
V
DS
= 20 V; I
D
= 2.2 A
2
4.5
-
S
I
D(ON)
On-state drain current
V
GS
= 10 V; V
DS
= 1 V;
3.5
-
-
A
V
GS
= 4.5 V; V
DS
= 5 V
2
-
-
A
I
DSS
Zero gate voltage drain
V
DS
= 24 V; V
GS
= 0 V;
-
10
100
nA
current
V
DS
= 24 V; V
GS
= 0 V; T
j
= 150C
-
0.6
10
A
I
GSS
Gate source leakage current V
GS
=
20 V; V
DS
= 0 V
-
10
100
nA
Q
g(tot)
Total gate charge
I
D
= 2.3 A; V
DD
= 15 V; V
GS
= 10 V
-
6
-
nC
Q
gs
Gate-source charge
-
0.7
-
nC
Q
gd
Gate-drain (Miller) charge
-
0.7
-
nC
t
d on
Turn-on delay time
V
DD
= 20 V; R
D
= 18
;
-
6
-
ns
t
r
Turn-on rise time
V
GS
= 10 V; R
G
= 6
-
8
-
ns
t
d off
Turn-off delay time
Resistive load
-
21
-
ns
t
f
Turn-off fall time
-
15
-
ns
L
d
Internal drain inductance
Measured tab to centre of die
-
2.5
-
nH
L
s
Internal source inductance
Measured from source lead to source
-
5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 20 V; f = 1 MHz
-
250
-
pF
C
oss
Output capacitance
-
88
-
pF
C
rss
Feedback capacitance
-
54
-
pF
February 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
BSP100
TrenchMOS
TM
transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
T
sp
= 25 C
-
-
6
A
(body diode)
I
SM
Pulsed source current (body
-
-
24
A
diode)
V
SD
Diode forward voltage
I
F
= 1.25 A; V
GS
= 0 V
-
0.82
1.2
V
t
rr
Reverse recovery time
I
F
= 1.25 A; -dI
F
/dt = 100 A/
s;
-
69
-
ns
Q
rr
Reverse recovery charge
V
GS
= 0 V; V
R
= 25 V
-
55
-
nC
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
sp
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
sp
); conditions: V
GS
10 V
Fig.3. Safe operating area. T
sp
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-sp
= f(t); parameter D = t
p
/T
0
20
40
60
80
100
120
140
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tsp / C
BSP100
0.1
1
10
100
1
10
100
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
d.c.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
0
20
40
60
80
100
120
140
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tsp / C
BSP100
0.01
0.1
1
10
100
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Peak Pulsed Drain Current, IDM (A)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
February 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
BSP100
TrenchMOS
TM
transistor
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
) ; parameter T
j
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
0
1
2
3
4
5
6
7
8
9
10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
3.2 V
3.4 V
4 V
Tj = 25 C
VGS = 20 V
3.6 V
3.8 V
5V
10 V
4.2 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
150 C
0
0.1
0.2
0.3
0.4
0.5
0
1
2
3
4
5
6
7
8
9
10
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS =5 V
4.2 V
20V
Tj = 25 C
3.8V
4 V
3.6 V
10V
3.2 V
3.4 V
-50
0
50
100
150
0
0.5
1
1.5
2
SOT223 30V Trench
Tj / C
a
Normalised RDS(ON) = f(Tj)
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
150 C
-60
-40
-20
0
20
40
60
80
100 120 140
Tj / C
VGS(TO) / V
4
3
2
1
0
max.
typ.
min.
February 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
BSP100
TrenchMOS
TM
transistor
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
p
);
unclamped inductive load
0
1
2
3
4
5
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
typ
min
max
0
1
2
3
4
5
6
7
8
9
10
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
Drain-Source Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
150 C
VGS = 0 V
10
100
1000
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
BSP100
0.1
1
10
1E-06
1E-05
1E-04
1E-03
1E-02
Avalanche time, tp (s)
Non-repetitive Avalanche current, IAS (A)
25 C
VDS
ID
tp
Tj prior to avalanche =125 C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 2.3A
Tj = 25 C
VDD = 15 V
February 1999
5
Rev 1.000