DATA SHEET
Product specification
File under Discrete Semiconductors, SC13b
April 1995
DISCRETE SEMICONDUCTORS
BSS123
N-channel enhancement mode
vertical D-MOS transistor
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSS123
FEATURES
Direct interface to C-MOS, TTL,
etc.
High-speed switching
No secondary breakdown.
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a SOT23
envelope, intended for use as a line
current interruptor in telephone sets
and for applications in relay,
high-speed and line transformer
drivers.
PINNING - SOT23
PIN
DESCRIPTION
1
gate
2
source
3
drain
QUICK REFERENCE DATA
PIN CONFIGURATION
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
V
DS
drain-source voltage
100
V
I
D
drain current
DC value
150
mA
R
DS(on)
drain-source on-resistance
I
D
= 120 mA
V
GS
= 10 V
6
V
GS(th)
gate-source threshold voltage I
D
= 1 mA
V
GS
= V
DS
2.8
V
Fig.1 Simplified outline and symbol.
Marking: SA.
ndbook, halfpage
MSB003
Top view
1
2
3
handbook, 2 columns
s
d
g
MBB076 - 1
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSS123
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
THERMAL RESISTANCE
Note
1. Device mounted on a FR4 printboard.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
drain-source voltage
-
100
V
V
GSO
gate-source voltage
open drain
-
20
V
I
D
drain current
DC value
-
150
mA
I
DM
drain current
peak value
-
600
mA
P
tot
total power dissipation
up to T
amb
= 25
C
-
250
mW
T
stg
storage temperature range
-
65
150
C
T
j
junction temperature
-
150
C
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-a
from junction to ambient (note 1)
500
K/W
April 1995
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSS123
CHARACTERISTICS
T
j
= 25
C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
V
(BR)DSS
drain-source breakdown voltage
I
D
= 10
A
V
GS
= 0
100
-
-
V
I
DSS
drain-source leakage current
V
DS
= 60 V
V
GS
= 0
-
-
10
nA
I
GSS
gate-source leakage current
V
GS
= 20 V
V
DS
= 0
-
-
10
nA
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA
V
GS
= V
DS
0.8
-
2.8
V
R
DS(on)
drain-source on-resistance
I
D
= 120 mA
V
GS
= 10 V
-
3
6
Y
fs
transfer admittance
I
D
= 120 mA
V
DS
= 25 V
80
140
-
mS
C
iss
input capacitance
V
DS
= 25 V
V
GS
= 0
f = 1 MHz
-
24
40
pF
C
oss
output capacitance
V
DS
= 25 V
V
GS
= 0
f = 1 MHz
-
15
25
pF
C
rss
feedback capacitance
V
DS
= 25 V
V
GS
= 0
f = 1 MHz
-
4
10
pF
Switching times (see Figs 2 and 3)
t
on
turn-on time
I
D
= 200 mA
V
DD
= 50 V
V
GS
= 0 to 10 V
-
4
10
ns
t
off
turn-off time
I
D
= 250 mA
V
DD
= 50 V
V
GS
= 0 to 10 V
-
10
20
ns
April 1995
5
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSS123
Fig.2 Switching time test circuit.
handbook, halfpage
MSA631
50
VDD = 50 V
ID
10 V
0 V
Fig.3 Input and output waveforms.
handbook, halfpage
MBB692
10 %
90 %
90 %
10 %
ton
toff
OUTPUT
INPUT
PDF 
ZIP