Document Outline
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- PINNING - SOT223
- PIN CONFIGURATION
- SYMBOL
- LIMITING VALUES
- AVALANCHE LIMITING VALUE
- THERMAL RESISTANCES
- STATIC CHARACTERISTICS
- DYNAMIC CHARACTERISTICS
- PRINTED CIRCUIT BOARD
- MECHANICAL DATA
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
Philips Semiconductors
Product specification
PowerMOS transistor
BUK482-200A
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel
enhancement
mode
SYMBOL
PARAMETER
MAX.
UNIT
field-effect power transistor in a
plastic envelope suitable for surface
V
DS
Drain-source voltage
200
V
mounting featuring high avalanche
I
D
Drain current (DC)
2.0
A
energy capability, stable blocking
P
tot
Total power dissipation
8.3
W
voltage, fast switching and high
R
DS(ON)
Drain-source on-state resistance
0.9
thermal
cycling
performance.
Intended for use in Switched Mode
Power Supplies (SMPS) and general
purpose switching applications.
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
4
drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
200
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
200
V
V
GS
Gate-source voltage
-
30
V
I
D
Drain current (DC)
T
sp
= 25 C
-
2.0
A
T
sp
= 100 C
-
1.3
A
I
DM
Drain current (pulse peak
T
sp
= 25 C
-
8.0
A
value)
I
DR
Source-drain diode current
T
sp
= 25 C
-
2.0
A
(DC)
I
DRM
Source-drain diode current
T
sp
= 25 C
-
8.0
A
(pulse peak value)
P
tot
Total power dissipation
T
sp
= 25 C
-
8.3
W
T
stg
Storage temperature
-55
150
C
T
j
Junction Temperature
-
150
C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 2 A ; V
DD
50 V ; V
GS
= 10 V ;
unclamped inductive turn-off
R
GS
= 50
energy
T
j
= 25C prior to surge
-
50
mJ
T
j
= 100C prior to surge
-
8
mJ
4
1
2
3
d
g
s
January 1998
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK482-200A
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
R
th j-sp
Thermal resistance junction to
-
-
15
K/W
solder point
R
th j-a
Thermal resistance junction to
pcb mounted; minimum footprint
-
156
-
K/W
ambient
pcb mounted; pad area as in fig:17
-
70
-
K/W
STATIC CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA
200
-
-
V
voltage
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 0.25 mA
2.0
3.0
4.0
V
I
DSS
Zero gate voltage drain current
V
DS
= 200 V; V
GS
= 0 V; T
j
= 25 C
-
0.1
10
A
V
DS
= 200 V; V
GS
= 0 V; T
j
= 125 C
-
0.1
1.0
mA
I
GSS
Gate source leakage current
V
GS
=
30 V; V
DS
= 0 V
-
10
100
nA
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 2 A
-
0.53
0.9
resistance
V
SD
Source-drain diode forward
I
F
= 2 A ;V
GS
= 0 V
-
0.87
1.0
V
voltage
DYNAMIC CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 2 A
0.5
2.6
-
S
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
305
400
pF
C
oss
Output capacitance
-
60
100
pF
C
rss
Feedback capacitance
-
24
50
pF
Q
g(tot)
Total gate charge
V
GS
= 10 V; I
D
= 2 A; V
DS
= 160 V
-
13
-
nC
Q
gs
Gate to source charge
-
2
-
nC
Q
gd
Gate to drain (Miller) charge
-
5
-
nC
t
d on
Turn-on delay time
V
DD
= 30 V; I
D
= 2.75 A;
-
10
15
ns
t
r
Turn-on rise time
V
GS
= 10 V; R
GS
= 50
;
-
30
45
ns
t
d off
Turn-off delay time
R
GEN
= 50
-
30
40
ns
t
f
Turn-off fall time
-
20
30
ns
t
rr
Source-drain diode reverse
I
F
= 2 A; -dI
F
/dt = 100 A/
s;
-
88
-
ns
recovery time
Q
rr
Source-drain diode reverse
V
GS
= 0 V; V
R
= 100 V
-
370
-
nC
recovery charge
January 1998
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK482-200A
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
amb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
amb
); conditions: V
GS
10 V
Fig.3. Transient thermal impedance.
Z
th j-sp
= f(t); parameter D = t
p
/T
Fig.4. Safe operating area. T
amb
= 25 C.
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tamb / C
1
10
100
1000
0.01
0.1
1
10
BUK482-200A
VDS / V
ID / A
RDS(ON) = VDS/ID
100 us
1 ms
10 ms
100 ms
DC
tp = 10 us
0
20
40
60
80
100
120
140
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tamb / C
0
2
4
6
8
10
0
2
4
6
8
10
BUK482-200A
VDS / V
ID / A
VGS = 20 V
10
4
4.5
5
5.5
6
6.5
1us
10us
100us
1ms
10ms
100ms
1s
10s
0.01
0.1
1
10
100
BUK482-200A
tp / sec
Zth(j-sp) K/W
D =
t
p
t
p
T
T
P
t
D
0
1
2
3
4
5
6
7
8
0
0.5
1
1.5
2
BUK482-200A
ID / A
RDS(ON) / Ohms
VGS =
5 V
5.5 V
6 V
6.5 V
10 V
20 V
January 1998
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK482-200A
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 2 A; V
GS
= 10 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
2
4
6
8
10
0
1
2
3
4
5
6
7
8
BUK482-200A
VGS / V
ID / A
Tj = 150 C
25 C
-60
-40
-20
0
20
40
60
80
100
120
140
Tj / C
VGS(TO) / V
4
3
2
1
0
max.
typ.
min.
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
BUK482-200A
ID / A
gfs / S
Tj = 25 C
150 C
0
1
2
3
4
VGS / V
ID / A
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
SUB-THRESHOLD CONDUCTION
typ
2 %
98 %
-60
-40
-20
0
20
40
60
80
100 120 140
Tj / C
Normalised RDS(ON) = f(Tj)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
a
0
50
100
150
200
1
10
100
1000
Crss
BUK482-200A
VDS / V
C / pF
Ciss
Coss
January 1998
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK482-200A
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 2 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
amb
); conditions: I
D
= 2 A
Fig.16. Avalanche energy test circuit.
0
5
10
15
20
0
5
10
15
BUK482-200A
Qg / nC
VGS / V
VDS = 40 V
160 V
20
40
60
80
100
120
140
Tamb/ C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
Normalised Avalanche Energy
0
0.5
1
1.5
0
1
2
3
4
5
6
7
8
BUK482-200A
VSDS / V
IF / A
Tj = 150 C
25 C
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
January 1998
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK482-200A
PRINTED CIRCUIT BOARD
Dimensions in mm.
Fig.17. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35
m thick).
36
60
9
10
4.6
18
4.5
7
15
50
January 1998
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK482-200A
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.11 g
Fig.18. SOT223 surface mounting package.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to surface mounting instructions for SOT223 envelope.
3. Epoxy meets UL94 V0 at 1/8".
6.7
6.3
3.1
2.9
4
1
2
3
2.3
1.05
0.85
0.80
0.60
4.6
3.7
3.3
7.3
6.7
B
A
0.10
0.02
13
16
max
1.8
max
10
max
0.32
0.24
(4x)
B
M
0.1
A
M
0.2
January 1998
7
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
BUK482-200A
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
January 1998
8
Rev 1.000
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