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Электронный компонент: BUK581-100A

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Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
Logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
SYMBOL
PARAMETER
MAX.
UNIT
logic level field-effect power
transistor in a plastic envelope
V
DS
Drain-source voltage
100
V
suitable for surface mount
I
D
Drain current (DC)
0.9
A
applications.
P
tot
Total power dissipation
1.5
W
The device is intended for use in
T
j
Junction temperature
150
C
automotive and general purpose
R
DS(ON)
Drain-source on-state
0.90
switching applications.
resistance;
V
GS
= 5 V
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
4
drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
-
100
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
100
V
V
GS
Gate-source voltage
-
-
15
V
I
D
Drain current (DC)
T
amb
= 25 C
-
0.9
A
I
D
Drain current (DC)
T
amb
= 100 C
-
0.6
A
I
DM
Drain current (pulse peak value)
T
amb
= 25 C
-
3.6
A
P
tot
Total power dissipation
T
amb
= 25 C
-
1.5
W
T
stg
Storage temperature
-
- 55
150
C
T
j
Junction Temperature
-
-
150
C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
R
th j-b
From junction to board
1
Mounted on any PCB
-
50
-
K/W
R
th j-amb
From junction to ambient
Mounted on PCB of Fig.17
-
-
85
K/W
4
1
2
3
d
g
s
1 Temperature measured 1-3 mm from tab.
January 1998
1
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA
100
-
-
V
voltage
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 0.1 mA
1.0
1.5
2.0
V
I
DSS
Zero gate voltage drain current
V
DS
= 100 V; V
GS
= 0 V;
-
1
10
A
I
DSS
Zero gate voltage drain current
V
DS
= 100 V; V
GS
= 0 V; T
j
= 125 C
-
0.1
1.0
mA
I
GSS
Gate source leakage current
V
GS
=
15 V; V
DS
= 0 V
-
10
100
nA
R
DS(ON)
Drain-source on-state
V
GS
= 5 V; I
D
= 0.9 A
-
0.51
0.90
resistance
DYNAMIC CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 0.9 A
1
1.8
-
S
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
180
300
pF
C
oss
Output capacitance
-
45
60
pF
C
rss
Feedback capacitance
-
16
25
pF
t
d on
Turn-on delay time
V
DD
= 30 V; I
D
= 3 A;
-
6
10
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
GS
= 50
;
-
45
55
ns
t
d off
Turn-off delay time
R
gen
= 50
-
15
25
ns
t
f
Turn-off fall time
-
20
30
ns
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
DR
Continuous reverse drain
-
-
-
0.9
A
current
I
DRM
Pulsed reverse drain current
-
-
-
3.6
A
V
SD
Diode forward voltage
I
F
= 0.9 A; V
GS
= 0 V
-
0.85
1.1
V
t
rr
Reverse recovery time
I
F
= 0.9 A; -dI
F
/dt = 100 A/
s;
-
40
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 30 V
-
100
-
nC
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 0.9 A; V
DD
25 V;
-
-
10
mJ
unclamped inductive turn-off
V
GS
= 5 V; R
GS
= 50
; T
amb
= 25 C
energy
January 1998
2
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
Logic level FET
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
amb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
amb
); conditions: V
GS
5 V
Fig.3. Transient thermal impedance.
Z
th j-amb
= f(t); parameter D = t
p
/T
Fig.4. Safe operating area T
amb
= 25 C
I
D
&
I
DM
=
f(V
DS
); I
DM
single pulse; parameter t
p
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tamb / C
1
100
VDS / V
ID / A
10
1
0.1
0.01
BUK581-100A
10
1 ms
10 ms
100 ms
1 s
RDS(ON) = VDS/ID
10 s
DC
tp = 100 us
0
20
40
60
80
100
120
140
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
Tamb / C
0
2
4
6
8
10
VDS / V
ID / A
BUK581-100A
5
4
3
2
1
0
3
3.5
4
4.5
5
10
VGS / V = 2.5
1E-07
1E-05
1E-03
1E-01
1E+01
1E+03
BUKX81
t / s
Zth j-amb / (K/W)
1E+02
1E+01
1E+00
1E-01
1E-02
0.5
0.2
0.1
0.05
0.02
D =
t
p
t
p
T
T
P
t
D
D =
0
2
4
ID / A
RDS(ON) / Ohm
BUK581-100A
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
3.5
4.5
5
1
3
5
2.5
3
4
VGS / V = 10
January 1998
3
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
Logic level FET
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 0.9 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 0.1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS
); conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
2
4
VGS / V
ID / A
BUK581-100A
5
4
3
2
1
0
1
3
5
150
Tj / C = 25
-60
-40
-20
0
20
40
60
80
100
120
140
Tj / C
VGS(TO) / V
2
1
0
max.
typ.
min.
0
2
4
ID / A
gfs / S
BUK581-100A
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1
3
5
0
0.4
0.8
1.2
1.6
2
2.4
VGS / V
ID / A
1E-02
1E-03
1E-04
1E-05
1E-06
1E-07
SUB-THRESHOLD CONDUCTION SIZE 1
2 %
typ
98 %
-60
-40
-20
0
20
40
60
80
100 120 140
Tj / C
Normalised RDS(ON) = f(Tj)
2.0
1.5
1.0
0.5
0
a
0
20
40
BUK581-100A
VDS / V
C / pF
Ciss
Coss
Crss
10
100
1000
10
30
January 1998
4
Rev 1.000
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
Logic level FET
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 0.9 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
amb
); conditions: I
D
= 0.9 A
Fig.16. Avalanche energy test circuit.
0
2
4
6
8
10
BUK581-100A
QG / nC
VGS / V
10
9
8
7
6
5
4
3
2
1
0
80
VDS / V =20
20
40
60
80
100
120
140
Tamb/ C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
Normalised Avalanche Energy
0
1
VSDS / V
IF / A
BUK581-100A
5
4
3
2
1
0
0.5
1.5
25
Tj / C = 150
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
January 1998
5
Rev 1.000