Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK7515-100A
Standard level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel
enhancement
mode
SYMBOL
PARAMETER
MAX.
UNIT
standard level field-effect power
transistor in a plastic envelope using
V
DS
Drain-source voltage
100
V
'trench' technology which features
I
D
Drain current (DC)
75
A
very low on-state resistance. It is
P
tot
Total power dissipation
230
W
intended for use in automotive and
T
j
Junction temperature
175
C
general
purpose
switching
R
DS(ON)
Drain-source on-state
15
m
applications.
resistance
V
GS
= 10 V
PINNING - TO220AB
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
-
100
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
100
V
V
GS
Gate-source voltage
-
-
20
V
I
D
Drain current (DC)
T
mb
= 25 C
-
75
A
I
D
Drain current (DC)
T
mb
= 100 C
-
53
A
I
DM
Drain current (pulse peak value)
T
mb
= 25 C
-
240
A
P
tot
Total power dissipation
T
mb
= 25 C
-
230
W
T
stg
, T
j
Storage & operating temperature
-
- 55
175
C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-mb
Thermal resistance junction to
-
-
0.65
K/W
mounting base
R
th j-a
Thermal resistance junction to
in free air
60
-
K/W
ambient
d
g
s
1 2 3
tab
December 1998
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK7515-100A
Standard level FET
STATIC CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
100
-
-
V
voltage
T
j
= -55C
89
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
2
3.0
4.0
V
T
j
= 175C
1
-
-
V
T
j
= -55C
-
-
4.4
V
I
DSS
Zero gate voltage drain current
V
DS
= 100 V; V
GS
= 0 V;
-
0.05
10
A
T
j
= 175C
-
-
500
A
I
GSS
Gate source leakage current
V
GS
=
20 V; V
DS
= 0 V
-
2
100
nA
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 25 A
-
12.0
15.0
m
resistance
T
j
= 175C
-
-
40.5
m
DYNAMIC CHARACTERISTICS
T
mb
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
4500
6000
pF
C
oss
Output capacitance
-
550
660
pF
C
rss
Feedback capacitance
-
305
400
pF
t
d on
Turn-on delay time
V
DD
= 30 V; R
load
=1.2
;
-
35
55
ns
t
r
Turn-on rise time
V
GS
= 10 V; R
G
= 10
-
85
125
ns
t
d off
Turn-off delay time
-
150
225
ns
t
f
Turn-off fall time
-
70
100
ns
L
d
Internal drain inductance
Measured from contact screw on
-
3.5
-
nH
tab to centre of die
L
d
Internal drain inductance
Measured from drain lead 6 mm
-
4.5
-
nH
from package to centre of die
L
s
Internal source inductance
Measured from source lead 6 mm
-
7.5
-
nH
from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
DR
Continuous reverse drain
-
-
75
A
current
I
DRM
Pulsed reverse drain current
-
-
240
A
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.85
1.2
V
I
F
= 75 A; V
GS
= 0 V
-
1.1
-
V
t
rr
Reverse recovery time
I
F
= 75 A; -dI
F
/dt = 100 A/
s;
-
80
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 30 V
-
0.35
-
C
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 35 A; V
DD
25 V;
-
-
120
mJ
unclamped inductive turn-off
V
GS
= 10 V; R
GS
= 50
; T
mb
= 25 C
energy
December 1998
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK7515-100A
Standard level FET
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0.00001
0.001
0.1
10
0.001
0.01
0.1
1
D =
t
p
t
p
T
T
P
t
D
Zth / (K/W)
t/S
D =
0.5
0.2
0.1
0.05
0.02
0
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
0
50
100
150
200
250
300
ID/A
VDS/V
VGS\V =
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
9.0
10.0
20.0
1
10
100
1
10
100
1000
ID/A
VDS/V
RDS(ON) = VDS/ID
tp =
100mS
10mS
1mS
100uS
1uS
DC
0
20
40
60
80
100
11
12
13
14
15
16
17
18
19
20
RDS(ON)/mOhm
ID/A
VGS/V =
5.5
6.0
6.5
7.0
8.0
10.0
December 1998
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK7515-100A
Standard level FET
Fig.7. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(V
GS
); conditions I
D
= 25 A;
Fig.8. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.9. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.10. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
Fig.11. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.12. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
5
10
15
20
10
11
12
13
14
15
16
RDS(ON)/mOhm
VGS/V
0.5
1
1.5
2
2.5
3
-100
-50
0
50
100
150
200
Tmb / degC
a
Rds(on) normalised to 25degC
0
1
2
3
4
5
6
7
0
20
40
60
80
100
ID/A
VGS/V
Tj/C =
175
25
BUK759-60
-100
-50
0
50
100
150
200
0
1
2
3
4
5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
20
40
60
80
100
0
10
20
30
40
50
60
70
80
90
gfs/S
ID/A
0
1
2
3
4
5
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
typ
2%
98%
December 1998
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK7515-100A
Standard level FET
Fig.13. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.14. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 25 A; parameter V
DS
Fig.15. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.16. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 75 A
Fig.17. Avalanche energy test circuit.
Fig.18. Switching test circuit.
0.01
0.1
1
10
100
0
1
2
3
4
5
6
7
8
9
10
11
Thousands pF
VDS/V
Ciss
Coss
Crss
20
40
60
80
100
120
140
160
180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0
20
40
60
80
100
120
0
2
4
6
8
10
12
VGS/V
QG/nC
VDS =
14V
80V
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
0
20
40
60
80
100
ID/A
VSDS/V
Tj/C =
175
25
RD
T.U.T.
VDD
RG
VDS
+
-
VGS
0
December 1998
5
Rev 1.100
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