Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9508-55
Logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
SYMBOL
PARAMETER
MAX.
UNIT
level field-effect power transistor in a
plastic
envelope
using
'trench'
V
DS
Drain-source voltage
55
V
technology. The device features very
I
D
Drain current (DC)
75
A
low on-state resistance and has
P
tot
Total power dissipation
187
W
integral zener diodes giving ESD
T
j
Junction temperature
175
C
protection up to 2kV. It is intended for
R
DS(ON)
Drain-source on-state
8
m
use in
automotive and general
resistance
V
GS
= 5 V
purpose switching applications.
PINNING - TO220AB
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
-
55
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
55
V
V
GS
Gate-source voltage
-
-
10
V
I
D
Drain current (DC)
T
mb
= 25 C
-
75
A
I
D
Drain current (DC)
T
mb
= 100 C
-
65
A
I
DM
Drain current (pulse peak value)
T
mb
= 25 C
-
240
A
P
tot
Total power dissipation
T
mb
= 25 C
-
187
W
T
stg
, T
j
Storage & operating temperature
-
- 55
175
C
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
C
Electrostatic discharge capacitor
Human body model
-
2
kV
voltage
(100 pF, 1.5 k
)
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-mb
Thermal resistance junction to
-
-
0.8
K/W
mounting base
R
th j-a
Thermal resistance junction to
in free air
60
-
K/W
ambient
d
g
s
1 2 3
tab
February 1997
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9508-55
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
55
-
-
V
voltage
T
j
= -55C
50
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1.0
1.5
2.0
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
-
2.3
V
I
DSS
Zero gate voltage drain current
V
DS
= 55 V; V
GS
= 0 V;
-
0.05
10
A
T
j
= 175C
-
-
500
uA
I
GSS
Gate source leakage current
V
GS
=
5 V; V
DS
= 0 V
-
0.02
1
A
T
j
= 175C
-
-
10
A
V
(BR)GSS
Gate-source breakdown
I
G
=
1 mA;
10
-
-
V
voltage
R
DS(ON)
Drain-source on-state
V
GS
= 5 V; I
D
= 25 A
-
6.5
8
m
resistance
T
j
= 175C
-
-
17
m
DYNAMIC CHARACTERISTICS
T
mb
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
40
90
-
S
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
5200
6900
pF
C
oss
Output capacitance
-
840
1000
pF
C
rss
Feedback capacitance
-
350
480
pF
t
d on
Turn-on delay time
V
DD
= 30 V; I
D
= 25 A;
-
45
60
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
G
= 10
-
120
170
ns
t
d off
Turn-off delay time
-
225
300
ns
t
f
Turn-off fall time
-
100
135
ns
L
d
Internal drain inductance
Measured from contact screw on
-
3.5
-
nH
tab to centre of die
L
d
Internal drain inductance
Measured from drain lead 6 mm
-
4.5
-
nH
from package to centre of die
L
s
Internal source inductance
Measured from source lead 6 mm
-
7.5
-
nH
from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
DR
Continuous reverse drain
-
-
75
A
current
I
DRM
Pulsed reverse drain current
-
-
240
A
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.85
1.2
V
I
F
= 75 A; V
GS
= 0 V
-
1.0
-
V
t
rr
Reverse recovery time
I
F
= 75 A; -dI
F
/dt = 100 A/
s;
-
65
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 30 V
-
0.18
-
C
February 1997
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9508-55
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 75 A; V
DD
25 V;
-
-
500
mJ
unclamped inductive turn-off
V
GS
= 5 V; R
GS
= 50
; T
mb
= 25 C
energy
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
VDS / V
ID / A
100 us
1 ms
10 ms
100 ms
1
10
100
1000
1
10
RDS(ON) = VDS/ID
DC
100
BUKX508-55
tp = 10 us
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1E-07
1E-05
1E-03
1E-01
1E+01
t / s
Zth / (K/W)
1E+00
1E-01
1E-02
1E-03
0
0.5
0.2
0.1
0.05
0.02
D =
t
p
t
p
T
T
P
t
D
February 1997
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9508-55
Logic level FET
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
0
2
4
6
8
10
0
20
40
60
80
100
VGS/V =
3.2
3.0
2.8
2.6
2.4
2.2
3.4
4.0
10
ID/A
VDS/V
0
20
40
60
80
100
0
10
20
30
40
50
60
70
80
90
100
110
120
gfs/S
ID/A
0
20
40
60
80
100
120
0
5
10
15
BUK9508-55
ID / A
RDS(ON) / mOhm
VGS / V =
3
3.2
3.4
3.6
4
5
10
-100
-50
0
50
100
150
200
0.5
1
1.5
2
2.5
BUK959-60
Tmb / degC
Rds(on) normlised to 25degC
a
0
1
2
3
4
0
20
40
60
80
100
Tj/C =
175
25
ID/A
VGS/V
BUK959-60
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
February 1997
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9508-55
Logic level FET
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 50 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 75 A
Fig.16. Avalanche energy test circuit.
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
0
0.2
0.4
0.6
0.8
1
1.2
0
20
40
60
80
100
Tj/C =
175
25
IF/A
VSDS/V
0.01
0.1
1
10
100
0
2
4
6
8
10
12
Thousands (pF)
VDS/V
Ciss
Coss
Crss
20
40
60
80
100
120
140
160
180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0
10
20
30
40
50
60
70
80
90
0
1
2
3
4
5
6
VGS/V
VDS = 14V
VDS = 44V
QG/nC
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
February 1997
5
Rev 1.000
PDF 
ZIP