BUK95/9608-55A
TrenchMOSTM logic level FET
Rev. 03 -- 6 May 2002
Product data
1.
Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOSTM technology, featuring very low on-state resistance.
Product availability:
BUK9508-55A in SOT78 (TO-220AB)
BUK9608-55A in SOT404 (D
2
-PAK).
2.
Features
s
TrenchMOSTM technology
s
Q101 compliant
s
175
C rated
s
Logic level compatible.
3.
Applications
s
Automotive and general purpose power switching:
x
12 V and 24 V loads
x
Motors, lamps and solenoids.
4.
Pinning information
[1]
It is not possible to make connection to pin 2 of the SOT404 package.
Table 1:
Pinning - SOT78 and SOT404, simplified outline and symbol
Pin
Description
Simplified outline
Symbol
1
gate (g)
SOT78 (TO-220AB)
SOT404 (D
2
-PAK)
2
drain (d)
[1]
3
source (s)
mb
mounting base;
connected to drain (d)
MBK106
1 2
mb
3
1
3
2
MBK116
mb
s
d
g
MBB076
Philips Semiconductors
BUK95/9608-55A
TrenchMOSTM logic level FET
Product data
Rev. 03 -- 6 May 2002
2 of 14
9397 750 09573
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5.
Quick reference data
6.
Limiting values
[1]
Current is limited by power dissipation chip rating
[2]
Continuous current is limited by package.
Table 2:
Quick reference data
Symbol Parameter
Conditions
Typ
Max
Unit
V
DS
drain-source voltage (DC)
-
55
V
I
D
drain current (DC)
T
mb
= 25
C; V
GS
= 5 V
-
125
A
P
tot
total power dissipation
T
mb
= 25
C
-
253
W
T
j
junction temperature
-
175
C
R
DSon
drain-source on-state resistance
T
j
= 25
C; V
GS
= 5 V; I
D
= 25 A
6.8
8
m
T
j
= 25
C; V
GS
= 4.5 V; I
D
= 25 A
-
8.5
m
T
j
= 25
C; V
GS
= 10 V; I
D
= 25 A
6.4
7.5
m
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
V
DS
drain-source voltage (DC)
-
55
V
V
DGR
drain-gate voltage (DC)
R
GS
= 20 k
-
55
V
V
GS
gate-source voltage (DC)
-
15
V
I
D
drain current (DC)
T
mb
= 25
C; V
GS
= 5 V;
Figure 2
and
3
[1]
-
125
A
[2]
-
75
A
T
mb
= 100
C; V
GS
= 5 V;
Figure 2
[2]
-
75
A
I
DM
peak drain current
T
mb
= 25
C; pulsed; t
p
10
s;
Figure 3
-
503
A
P
tot
total power dissipation
T
mb
= 25
C;
Figure 1
-
253
W
T
stg
storage temperature
-
55
+175
C
T
j
junction temperature
-
55
+175
C
Source-drain diode
I
DR
reverse drain current (DC)
T
mb
= 25
C
[1]
-
125
A
[2]
-
75
A
I
DRM
peak reverse drain current
T
mb
= 25
C; pulsed; t
p
10
s
-
503
A
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source avalanche
energy
unclamped inductive load; I
D
= 75 A;
V
DS
55 V; V
GS
= 5 V; R
GS
= 50
;
starting T
mb
= 25
C
-
670
mJ
Philips Semiconductors
BUK95/9608-55A
TrenchMOSTM logic level FET
Product data
Rev. 03 -- 6 May 2002
3 of 14
9397 750 09573
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
V
GS
4.5 V
Fig 1.
Normalized total power dissipation as a
function of mounting base temperature.
Fig 2.
Continuous drain current as a function of
mounting base temperature.
T
mb
= 25
C; I
DM
single pulse.
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
03na19
0
40
80
120
0
50
100
150
200
Tmb
(
C)
Pder
(%)
03ni52
0
50
100
150
25
50
75
100
125
150
175
200
Tmb (C)
ID
(A)
Capped at 75 A due to package
P
der
P
tot
P
tot 25 C
(
)
-----------------------
100%
=
03ni50
1
10
102
103
10-1
1
10
102
VDS (V)
ID
(A)
DC
100 ms
10 ms
Limit RDSon = VDS/ID
1 ms
tp = 10 s
100 s
Capped at 75 A due to package
Philips Semiconductors
BUK95/9608-55A
TrenchMOSTM logic level FET
Product data
Rev. 03 -- 6 May 2002
4 of 14
9397 750 09573
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
7.
Thermal characteristics
7.1 Transient thermal impedance
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
R
th(j-mb)
thermal resistance from junction to
mounting base
Figure 4
-
-
0.59
K/W
R
th(j-a)
thermal resistance from junction to ambient
SOT78
vertical in still air
-
60
-
K/W
SOT404
mounted on a printed circuit board;
minimum footprint
-
50
-
K/W
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration.
03ni51
single shot
0.2
0.1
0.05
0.02
10-3
10-2
10-1
1
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Zth(j-mb)
(K/W)
= 0.5
tp
tp
T
P
t
T
=
Philips Semiconductors
BUK95/9608-55A
TrenchMOSTM logic level FET
Product data
Rev. 03 -- 6 May 2002
5 of 14
9397 750 09573
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
8.
Characteristics
Table 5:
Characteristics
T
j
= 25
C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V
(BR)DSS
drain-source breakdown
voltage
I
D
= 0.25 mA; V
GS
= 0 V
T
j
= 25
C
55
-
-
V
T
j
=
-
55
C
50
-
-
V
V
GS(th)
gate-source threshold voltage I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
C
1
1.5
2
V
T
j
= 175
C
0.5
-
-
V
T
j
=
-
55
C
-
-
2.3
V
I
DSS
drain-source leakage current
V
DS
= 55 V; V
GS
= 0 V
T
j
= 25
C
-
0.05
10
A
T
j
= 175
C
-
-
500
A
I
GSS
gate-source leakage current
V
GS
=
10 V; V
DS
= 0 V
-
2
100
nA
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
C
-
6.8
8
m
T
j
= 175
C
-
-
16
m
V
GS
= 4.5 V; I
D
= 25 A
-
-
8.5
m
V
GS
= 10 V; I
D
= 25 A
-
6.4
7.5
m
Dynamic characteristics
Q
g(tot)
total gate charge
V
GS
= 5 V; V
DD
= 44 V;
I
D
= 25 A;
Figure 14
-
92
-
nC
Q
gs
gate-to-source charge
-
11
-
nC
Q
gd
gate-to-drain (Miller) charge
-
43
-
nC
C
iss
input capacitance
V
GS
= 0 V; V
DS
= 25 V;
f = 1 MHz;
Figure 12
-
4551
6021
pF
C
oss
output capacitance
-
760
900
pF
C
rss
reverse transfer capacitance
-
500
687
pF
t
d(on)
turn-on delay time
V
DD
= 30 V; R
L
= 1.2
;
V
GS
= 5 V; R
G
= 10
-
40
-
ns
t
r
rise time
-
175
-
ns
t
d(off)
turn-off delay time
-
280
-
ns
t
f
fall time
-
167
-
ns
L
d
internal drain inductance
from drain lead 6 mm from
package to centre of die
-
4.5
-
nH
from contact screw on
mounting base to centre of
die SOT78
-
3.5
-
nH
from upper edge of drain
mounting base to centre of
die SOT404
-
2.5
-
nH
L
s
internal source inductance
from source lead to source
bond pad
-
7.5
-
nH
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