Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9635-100A
Logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
SYMBOL
PARAMETER
MAX.
UNIT
level field-effect power transistor in a
plastic envelope suitable for surface
V
DS
Drain-source voltage
100
V
mounting. Using 'trench' technology
I
D
Drain current (DC)
40
A
the device features very low on-state
P
tot
Total power dissipation
150
W
resistance. It is intended for use in
T
j
Junction temperature
175
C
automotive and general purpose
R
DS(ON)
Drain-source on-state
switching applications.
resistance
V
GS
= 5 V
35
m
V
GS
= 10 V
34
m
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
(no connection possible)
3
source
mb
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
-
100
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
100
V
V
GS
Gate-source voltage
-
-
10
V
V
GSM
Non Repetive gate-source voltage
-
-
15
V
I
D
Drain current (DC)
T
mb
= 25 C
-
40
A
I
D
Drain current (DC)
T
mb
= 100 C
-
29
A
I
DM
Drain current (pulse peak value)
T
mb
= 25 C
-
133
A
P
tot
Total power dissipation
T
mb
= 25 C
-
150
W
T
stg
, T
j
Storage & operating temperature
-
- 55
175
C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-mb
Thermal resistance junction to
-
-
1.01
K/W
mounting base
R
th j-a
Thermal resistance junction to
Minimum footprint, FR4
50
-
K/W
ambient
board
d
g
s
1
3
mb
2
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9635-100A
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
100
-
-
V
voltage
T
j
= -55C
89
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1
1.5
2
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
2.3
V
I
DSS
Zero gate voltage drain current
V
DS
= 100 V; V
GS
= 0 V;
-
0.05
10
A
T
j
= 175C
-
-
500
A
I
GSS
Gate source leakage current
V
GS
=
10 V; V
DS
= 0 V
-
2
100
nA
R
DS(ON)
Drain-source on-state
V
GS
= 5 V; I
D
= 25 A
-
26
35
m
resistance
T
j
= 175C
-
-
95
m
V
GS
= 10 V; I
D
= 25 A
-
24.1
34
m
V
GS
= 4.5 V; I
D
= 25 A
-
26.1
38
m
DYNAMIC CHARACTERISTICS
T
mb
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
2700
3500
pF
C
oss
Output capacitance
-
260
314
pF
C
rss
Feedback capacitance
-
160
220
pF
t
d on
Turn-on delay time
V
DD
= 30 V; R
load
=1.2
;
-
10
15
ns
t
r
Turn-on rise time
V
GS
= 10 V; R
G
= 10
-
62
87
ns
t
d off
Turn-off delay time
-
194
291
ns
t
f
Turn-off fall time
-
108
162
ns
L
d
Internal drain inductance
Measured from upper edge of drain
-
2.5
-
nH
tab to centre of die
L
s
Internal source inductance
Measured from source lead
-
7.5
-
nH
soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
DR
Continuous reverse drain
-
-
40
A
current
I
DRM
Pulsed reverse drain current
-
-
133
A
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.85
1.2
V
I
F
= 40 A; V
GS
= 0 V
-
1.1
-
V
t
rr
Reverse recovery time
I
F
= 40 A; -dI
F
/dt = 100 A/
s;
-
60
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 30 V
-
0.3
-
C
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 40 A; V
DD
25 V;
-
-
125
mJ
unclamped inductive turn-off
V
GS
= 10 V; R
GS
= 50
; T
mb
= 25 C
energy
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9635-100A
Logic level FET
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1E-07
1E-05
1E-3
1E-01
1E+01
0.001
0.01
0.1
1
10
D =
t
p
t
p
T
T
P
t
D
D=
0.5
0.2
0.1
0.05
0.02
0
Zth/(K/W)
t/S
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
0
50
100
150
10.0
5.0
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
ID/A
VDS/V
VGS/V=
1
10
100
1000
1
10
100
1000
ID/A
VDS/V
DC
RDS(ON)=VDS/ID
tp=
1uS
10uS
100uS
1mS
10mS
100mS
0
10
20
30
40
50
60
70
20
25
30
35
40
ID/A
RDS(ON)/mOhm
VGS/V=
3.0
3.2
3.4
3.6
4.0
5.0
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9635-100A
Logic level FET
Fig.7. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(V
GS
); conditions: I
D
= 25 A;
Fig.8. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.9. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.10. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
Fig.11. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.12. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
3
4
5
6
7
8
9
10
22
23
24
25
26
27
28
29
30
31
32
33
ID/A
RDS(ON)/mOhm
0.5
1
1.5
2
2.5
3
-100
-50
0
50
100
150
200
Tmb / degC
a
Rds(on) normalised to 25degC
0.0
1.0
2.0
3.0
4.0
5.0
0
10
20
30
40
50
60
70
80
90
ID/A
VGS/V
Tj/C=
175
25
BUK959-60
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
20
40
60
80
100
0
10
20
30
40
50
60
70
ID/A
gfs/S
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
BUK9635-100A
Logic level FET
Fig.13. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.14. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 25 A; parameter V
DS
Fig.15. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.16. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 75 A
Fig.17. Avalanche energy test circuit.
Fig.18. Switching test circuit.
0.01
0.1
1
10
100
0
1
2
3
4
5
6
7
Thousands pF
VDS/V
Ciss
Coss
Crss
20
40
60
80
100
120
140
160
180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0
1
2
3
4
5
6
0
10
20
30
40
QG / nC
VGS / V
VDS = 14V
VDS = 44V
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
0.0
0.5
1.0
1.5
0
20
40
60
80
100
Tj/C=
175
25
RD
T.U.T.
VDD
RG
VDS
+
-
VGS
0
August 1999
5
Rev 1.000
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