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BUK95/964R2-55B
TrenchMOSTM logic level FET
Rev. 02 -- 8 October 2002
Product data
1.
Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive TrenchMOSTM technology.
Product availability:
BUK954R2-55B in SOT78 (TO-220AB)
BUK964R2-55B in SOT404 (D
2
-PAK).
1.2 Features
1.3 Applications
1.4 Quick reference data
2.
Pinning information
[1]
It is not possible to make connection to pin 2 of the SOT404 package.
s
Very low on-state resistance
s
Q101 compliant
s
175
C rated
s
Logic level compatible.
s
Automotive systems
s
12 V and 24 V loads
s
Motors, lamps and solenoids
s
General purpose power switching.
s
E
DS(AL)S
1.2 J
s
R
DSon
= 3.5 m
(typ)
s
I
D
75 A
s
P
tot
300 W.
Table 1:
Pinning - SOT78 and SOT404 simplified outlines and symbol
Pin
Description
Simplified outline
Symbol
1
gate (g)
SOT78 (TO-220AB)
SOT404 (D
2
-PAK)
2
drain (d)
[1]
3
source (s)
mb
mounting base,
connected to
drain (d)
MBK106
1 2
mb
3
1
3
2
MBK116
mb
s
d
g
MBB076
Philips Semiconductors
BUK95/964R2-55B
TrenchMOSTM logic level FET
Product data
Rev. 02 -- 8 October 2002
2 of 15
9397 750 10277
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
3.
Limiting values
[1]
Current is limited by power dissipation chip rating
[2]
Continuous current is limited by package
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
V
DS
drain-source voltage (DC)
-
55
V
V
DGR
drain-gate voltage (DC)
R
GS
= 20 k
-
55
V
V
GS
gate-source voltage (DC)
-
15
V
I
D
drain current (DC)
T
mb
= 25
C; V
GS
= 5 V;
Figure 2
and
3
[1]
-
191
A
[2]
-
75
A
T
mb
= 100
C; V
GS
= 5 V;
Figure 2
[2]
-
75
A
I
DM
peak drain current
T
mb
= 25
C; pulsed; t
p
10
s;
Figure 3
-
765
A
P
tot
total power dissipation
T
mb
= 25
C;
Figure 1
-
300
W
T
stg
storage temperature
-
55
+175
C
T
j
junction temperature
-
55
+175
C
Source-drain diode
I
DR
reverse drain current (DC)
T
mb
= 25
C
[1]
-
191
A
[2]
-
75
A
I
DRM
peak reverse drain current
T
mb
= 25
C; pulsed; t
p
10
s
-
765
A
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source avalanche
energy
unclamped inductive load; I
D
= 75 A;
V
DS
55 V; V
GS
= 5 V; R
GS
= 50
;
starting T
mb
= 25
C
-
1.2
J
Philips Semiconductors
BUK95/964R2-55B
TrenchMOSTM logic level FET
Product data
Rev. 02 -- 8 October 2002
3 of 15
9397 750 10277
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
V
GS
5 V
Fig 1.
Normalized total power dissipation as a
function of mounting base temperature.
Fig 2.
Continuous drain current as a function of
mounting base temperature.
T
mb
= 25
C; I
DM
single pulse.
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
03na19
0
40
80
120
0
50
100
150
200
Tmb
(
C)
Pder
(%)
03ng54
0
50
100
150
200
25
50
75
100
125
150
175
200
Tmb (C)
ID
(A)
Capped at 75 A due to package
P
der
P
tot
P
tot 25 C
(
)
-----------------------
100%
=
03ng55
1
10
102
103
10-1
1
10
102
VDS (V)
ID
(A)
DC
100 ms
10 ms
1 ms
tp = 10 s
100 s
Capped at 75 A due to package
Limit RDSon = VDS/ID
Philips Semiconductors
BUK95/964R2-55B
TrenchMOSTM logic level FET
Product data
Rev. 02 -- 8 October 2002
4 of 15
9397 750 10277
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
4.
Thermal characteristics
4.1 Transient thermal impedance
Table 3:
Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
R
th(j-mb)
thermal resistance from junction to
mounting base
Figure 4
-
-
0.5
K/W
R
th(j-a)
thermal resistance from junction to
ambient
SOT78
vertical in still air
-
60
-
K/W
SOT404
mounted on a printed circuit board; minimum
footprint
-
50
-
K/W
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration.
03ng56
single shot
0.2
0.1
0.05
0.02
10-3
10-2
10-1
1
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Zth(j-mb)
(K/W)
= 0.5
tp
tp
T
P
t
T
=
Philips Semiconductors
BUK95/964R2-55B
TrenchMOSTM logic level FET
Product data
Rev. 02 -- 8 October 2002
5 of 15
9397 750 10277
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5.
Characteristics
Table 4:
Characteristics
T
j
= 25
C unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V
(BR)DSS
drain-source breakdown
voltage
I
D
= 0.25 mA; V
GS
= 0 V
T
j
= 25
C
55
-
-
V
T
j
=
-
55
C
50
-
-
V
V
GS(th)
gate-source threshold voltage I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
C
1.1
1.5
2
V
T
j
= 175
C
0.5
-
-
V
T
j
=
-
55
C
-
-
2.3
V
I
DSS
drain-source leakage current
V
DS
= 55 V; V
GS
= 0 V
T
j
= 25
C
-
0.02
1
A
T
j
= 175
C
-
-
500
A
I
GSS
gate-source leakage current
V
GS
=
15 V; V
DS
= 0 V
-
2
100
nA
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
C
-
3.5
4.2
m
T
j
= 175
C
-
-
8.4
m
V
GS
= 4.5 V; I
D
= 25 A
-
-
4.4
m
V
GS
= 10 V; I
D
= 25 A
-
3.1
3.7
m
Dynamic characteristics
Q
g(tot)
total gate charge
V
GS
= 5 V; V
DD
= 44 V;
I
D
= 25 A;
Figure 14
-
95
-
nC
Q
gs
gate-to-source charge
-
17
-
nC
Q
gd
gate-to-drain (Miller) charge
-
37
-
nC
C
iss
input capacitance
V
GS
= 0 V; V
DS
= 25 V;
f = 1 MHz;
Figure 12
-
7665
10220
pF
C
oss
output capacitance
-
1044
1253
pF
C
rss
reverse transfer capacitance
-
466
638
pF
t
d(on)
turn-on delay time
V
DD
= 30 V; R
L
= 1.2
;
V
GS
= 5 V; R
G
= 10
-
63
-
ns
t
r
rise time
-
232
-
ns
t
d(off)
turn-off delay time
-
273
-
ns
t
f
fall time
-
178
-
ns
L
d
internal drain inductance
from drain lead 6 mm from
package to centre of die
-
4.5
-
nH
from contact screw on
mounting base to centre of
die SOT78
-
3.5
-
nH
from upper edge of drain
mounting base to centre of
die SOT404
-
2.5
-
nH
L
s
internal source inductance
from source lead to source
bond pad
-
7.5
-
nH
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