DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4015B
MSI
Dual 4-bit static shift register
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
Dual 4-bit static shift register
HEF4015B
MSI
DESCRIPTION
The HEF4015B is a dual edge-triggered 4-bit static shift
register (serial-to-parallel converter). Each shift register
has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (O
0
to O
3
) and an overriding
asynchronous master reset input (MR). Information
present on D is shifted to the first register position, and all
the data in the register is shifted one position to the right
on the LOW-to-HIGH transition of CP. A HIGH on MR
clears the register and forces O
0
to O
3
to LOW,
independent of CP and D. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
Fig.1 Functional diagram.
HEF4015BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4015BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4015BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
APPLICATION INFORMATION
Some examples of applications for the HEF4015B are:
Serial-to-parallel converter
Buffer stores
General purpose register
D
A
, D
B
serial data input
MR
A
, MR
B
master reset input (active HIGH)
CP
A
, CP
B
clock input (LOW-to-HIGH
edge-triggered)
O
0A
, O
1A
, O
2A
, O
3A
parallel outputs
O
0B
, O
1B
, O
2B
, O
3B
parallel outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
3
Philips Semiconductors
Product specification
Dual 4-bit static shift register
HEF4015B
MSI
LOGIC DIAGRAM (one register)
Fig.3 Logic diagram.
FUNCTION TABLE
INPUTS
OUTPUTS
n
CP
D
MR
O
0
O
1
O
2
O
3
1
D
1
L
D
1
X
X
X
2
D
2
L
D
2
D
1
X
X
3
D
3
L
D
3
D
2
D
1
X
4
D
4
L
D
4
D
3
D
2
D
1
X
L
no change
X
X
H
L
L
L
L
Note
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4.
= positive-going transition
5.
= negative-going transition
6. D
n
= either HIGH or LOW
7. n
= number of clock pulse transitions
January 1995
4
Philips Semiconductors
Product specification
Dual 4-bit static shift register
HEF4015B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
C; C
L
= 50 pF; input transition times
20 ns
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP
O
n
5
130
260
ns
103 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
55
110
ns
44 ns
+
(0,23 ns/pF) C
L
15
40
80
ns
32 ns
+
(0,16 ns/pF) C
L
5
120
240
ns
93 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
55
110
ns
44 ns
+
(0,23 ns/pF) C
L
15
40
80
ns
32 ns
+
(0,16 ns/pF) C
L
MR
O
n
5
105
210
ns
78 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
45
90
ns
34 ns
+
(0,23 ns/pF) C
L
15
35
70
ns
27 ns
+
(0,16 ns/pF) C
L
Output transition times
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
HIGH to LOW
10
t
THL
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
LOW to HIGH
10
t
TLH
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
Set-up time
5
25
-
15
ns
see waveforms Figs 4 and 5
D
CP
10
t
su
25
-
10
ns
15
20
-
5
ns
Hold time
5
40
20
ns
D
CP
10
t
hold
20
10
ns
15
15
8
ns
Minimum clock
5
60
30
ns
pulse width; LOW
10
t
WCPL
30
15
ns
15
20
10
ns
Minimum MR
5
80
40
ns
pulse width; HIGH
10
t
WMRH
30
15
ns
15
24
12
ns
Recovery time
5
50
20
ns
for MR
10
t
RMR
30
10
ns
15
20
5
ns
Maximum clock
5
7
15
MHz
pulse frequency
10
f
max
15
30
MHz
15
22
44
MHz
January 1995
5
Philips Semiconductors
Product specification
Dual 4-bit static shift register
HEF4015B
MSI
V
DD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
1 500 f
i
+
(f
o
C
L
)
V
DD
2
where
dissipation per
10
6 300 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
17 000 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
Fig.4
Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery time for MR and minimum MR pulse width.
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