DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4016B
gates
Quadruple bilateral switches
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B
gates
DESCRIPTION
The HEF4016B has four independent analogue switches
(transmission gates). Each switch has two input/output
terminals (Y/Z) and an active HIGH enable input (E). When
E is connected to V
DD
a low impedance bidirectional path
between Y and Z is established (ON condition). When E is
connected to V
SS
the switch is disabled and a high
impedance between Y and Z is established (OFF
condition). Current through a switch will not cause
additional V
DD
current provided the voltage at the
terminals of the switch is maintained within the supply
voltage range; V
DD
(V
Y
, V
Z
)
V
SS
. Inputs Y and Z are
electrically equivalent terminals.
Fig.1 Functional diagram.
HEF4016BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4016BD(F):
14-lead DIL; ceramic (cerdip) (SOT73)
HEF4016BT(D):
14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
APPLICATION INFORMATION
Some examples of applications for the HEF4016B are:
Signal gating
Modulation
Demodulation
Chopper
E
0
to E
3
enable inputs
Y
0
to Y
3
input/output terminals
Z
0
to Z
3
input/output terminals
Fig.3 Schematic diagram
(one switch).
January 1995
3
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B
gates
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
DC CHARACTERISTICS
T
amb
= 25
C; V
SS
= 0 V (unless otherwise specified)
Power dissipation per switch
P
max.
100
mW
For other RATINGS see Family Specifications
PARAMETER
V
DD
V
SYMBOL
TYP.
MAX.
UNIT
CONDITIONS
5
8000
-
E
n
at V
IH
; V
is
= 0 to V
DD
; see Fig.4
ON resistance
10
R
ON
230
690
15
115
350
5
140
425
E
n
at V
IH
; V
is
= V
SS
; see Fig.4
ON resistance
10
R
ON
65
195
15
50
145
5
170
515
E
n
at V
IH
; V
is
= V
DD
; see Fig.4
ON resistance
10
R
ON
95
285
15
75
220
`
' ON resistance
5
200
-
E
n
at V
IH
; V
is
= 0 to V
DD
; see Fig.4
between any two
10
R
ON
15
-
channels
15
10
-
PARAMETER
V
DD
V
SYMBOL
T
amb
(
C)
UNIT
-
40
+
25
+
85
CONDITION
MIN.
MAX. MIN. MAX. MIN. MAX.
Quiescent
5
-
1,0
-
1,0
-
7,5
A
V
SS
= 0; all valid
input combinations;
V
I
= V
SS
or V
DD
device
10
I
DD
-
2,0
-
2,0
-
15,0
A
current
15
-
4,0
-
4,0
-
30,0
A
Input leakage
15
I
IN
-
-
-
300
-
1000
nA
E
n
at V
SS
or V
DD
current at E
n
OFF-state leakage
5
-
-
-
-
-
-
nA
E
n
at V
IL
;
V
is
= V
SS
or V
DD
;
V
os
= V
DD
or V
SS
current, any
10
I
OZ
-
-
-
-
-
-
nA
channel OFF
15
-
-
-
200
-
-
nA
E
n
input
5
-
1,5
-
1,5
-
1,5
V
switch OFF; see
Fig.9 for I
OZ
voltage LOW
10
V
IL
-
3,0
-
3,0
-
3,0
V
15
-
4,0
-
4,0
-
4,0
V
E
n
input
5
3,5
-
3,5
-
3,5
-
V
low-impedance
between Y and Z (ON
condition)
see R
ON
switch
voltage HIGH
10
V
IH
7,0
-
7,0
-
7,0
-
V
15
11,0
-
11,0
-
11,0
-
V
January 1995
4
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B
gates
Fig.4 Test set-up for measuring R
ON
.
Fig.5 Typical R
ON
as a function of input voltage.
E
n
>
V
IH
I
is
= 100
A
V
SS
= 0 V
January 1995
5
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B
gates
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
C; input transition times
20 ns
V
DD
V
SYMBOL
TYP.
MAX.
Propagation delays
V
is
V
os
5
25
50
ns
note 1
HIGH to LOW
10
t
PHL
10
20
ns
15
5
10
ns
5
20
40
ns
note 1
LOW to HIGH
10
t
PLH
10
20
ns
15
5
10
ns
Output disable times
E
n
V
os
5
90
130
ns
note 2
HIGH
10
t
PHZ
80
110
ns
15
75
100
ns
5
85
120
ns
note 2
LOW
10
t
PLZ
75
100
ns
15
75
100
ns
Output enable times
E
n
V
os
5
40
80
ns
note 2
HIGH
10
t
PZH
20
40
ns
15
15
30
ns
5
40
80
ns
note 2
LOW
10
t
PZL
20
40
ns
15
15
30
ns
Distortion, sine-wave
5
-
%
note 3
response
10
0,08
%
15
0,04
%
Crosstalk between
5
-
MHz
note 4
any two channels
10
1
MHz
15
-
MHz
Crosstalk; enable
5
-
mV
note 5
input to output
10
50
mV
15
-
mV
OFF-state
5
-
MHz
note 6
feed-through
10
1
MHz
15
-
MHz
ON-state frequency
5
-
MHz
note 7
response
10
90
MHz
15
-
MHz
January 1995
6
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B
gates
Notes
V
is
is the input voltage at a Y or Z terminal, whichever is assigned as input.
V
os
is the output voltage at a Y or Z terminal, whichever is assigned as output.
1. R
L
= 10 k
to V
SS
; C
L
= 50 pF to V
SS
; E
n
= V
DD
; V
is
= V
DD
(square-wave); see Figs 6 and 10.
2. R
L
= 10 k
; C
L
= 50 pF to V
SS
; E
n
= V
DD
(square-wave);
V
is
= V
DD
and R
L
to V
SS
for t
PHZ
and t
PZH
;
V
is
= V
SS
and R
L
to V
DD
for t
PLZ
and t
PZL
; see Figs 6 and 11.
3. R
L
= 10 k
; C
L
= 15 pF; E
n
= V
DD
; V
is
=
1
/
2
V
DD(p-p)
(sine-wave, symmetrical about
1
/
2
V
DD
);
f
is
= 1 kHz; see Fig.7.
4. R
L
= 1 k
; V
is
=
1
/
2
V
DD(p-p)
(sine-wave, symmetrical about
1
/
2
V
DD
);
5. R
L
= 10 k
to V
SS
; C
L
= 15 pF to V
SS
; E
n
= V
DD
(square-wave); crosstalk is
V
os
(peak value);
see Fig.6.
6. R
L
= 1 k
; C
L
= 5 pF; E
n
= V
SS
; V
is
=
1
/
2
V
DD(p-p)
(sine-wave, symmetrical about
1
/
2
V
DD
);
7. R
L
= 1 k
; C
L
= 5 pF; E
n
= V
DD
; V
is
=
1
/
2
V
DD(p-p)
(sine-wave, symmetrical about
1
/
2
V
DD
);
Note
1. All enable inputs switching.
V
DD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
550 f
i
+
(f
o
C
L
)
V
DD
2
where
dissipation per
10
2 600 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
(1)
15
6 500 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
20 log
V
os
(B)
V
is
(A)
-------------------
50 dB; E
n
(A)
V
SS
E
;
n
(B)
=
=
V
DD
see Fig. 8.
;
=
20 log
V
os
V
is
---------
50 dB; see Fig. 7.
=
20 log
V
os
V
is
---------
3 dB; see Fig. 7.
=
January 1995
7
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B
gates
Fig.6
Fig.7
Fig.8
Fig.9
January 1995
8
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B
gates
Fig.10 Waveforms showing propagation delays from V
is
to V
os
.
Fig.11 Waveforms showing output disable and enable times.
(1) V
is
at V
DD
(2) V
is
at V
SS
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