DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4556B
MSI
Dual 1-of-4 decoder/demultiplexer
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
Dual 1-of-4 decoder/demultiplexer
HEF4556B
MSI
DESCRIPTION
The HEF4556B is a dual 1-of-4 decoder/demultiplexer.
Each has two address inputs (A
0
and A
1
), an active LOW
enable input (E) and four mutually exclusive outputs which
are active LOW (O
0
to O
3
). When used as a decoder,
E when HIGH, forces O
0
to O
3
HIGH. When used as a
demultiplexer, the appropriate output is selected by the
information on A
0
and A
1
with E as data input. All
unselected outputs are HIGH.
Fig.1 Functional diagram.
PINNING
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF4556BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4556BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4556BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
E
enable inputs (active LOW)
A
0
and A
1
address inputs
O
0
to O
3
outputs (active LOW)
Fig.2 Pinning diagram.
January 1995
3
Philips Semiconductors
Product specification
Dual 1-of-4 decoder/demultiplexer
HEF4556B
MSI
TRUTH TABLE
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
INPUTS
OUTPUTS
E
A
0
A
1
O
0
O
1
O
2
O
3
L
L
L
L
H
H
H
L
H
L
H
L
H
H
L
L
H
H
H
L
H
L
H
H
H
H
H
L
H
X
X
H
H
H
H
Fig.3 Logic diagram (one decoder/multiplexer).
January 1995
4
Philips Semiconductors
Product specification
Dual 1-of-4 decoder/demultiplexer
HEF4556B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
C; C
L
= 50 pF; input transition times
20 ns
APPLICATION INFORMATION
Some examples of applications for the HEF4556B are:
Code conversion.
Address decoding.
Demultiplexing: when using the enable input as data input.
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
A
n
O
n
5
130
255
ns
103 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
50
100
ns
39 ns
+
(0,23 ns/pF) C
L
15
35
65
ns
27 ns
+
(0,16 ns/pF) C
L
5
105
210
ns
78 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
40
85
ns
29 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
E
n
O
n
5
120
240
ns
93 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
45
90
ns
34 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
5
105
205
ns
78 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
40
80
ns
29 ns
+
(0,23 ns/pF) C
L
15
30
60
ns
22 ns
+
(0,16 ns/pF) C
L
Output transition times
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
HIGH to LOW
10
t
THL
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
5
60
120
ns
10 ns
+
(1,0 ns/pF) C
L
LOW to HIGH
10
t
TLH
30
60
ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40
ns
6 ns
+
(0,28 ns/pF) C
L
V
DD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
4400 f
i
+
(f
o
C
L
)
V
DD
2
where
dissipation per
10
18 000 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
43 300 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
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