DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4585B
MSI
4-bit magnitude comparator
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995
2
Philips Semiconductors
Product specification
4-bit magnitude comparator
HEF4585B
MSI
DESCRIPTION
The HEF4585B is a 4-bit magnitude comparator which
compares two 4-bit words (A and B), whether they are `less
than', `equal to', or `greater than'. Each word has four
parallel inputs (A
0
to A
3
and B
0
to B
3
); A
3
and B
3
being the
most significant inputs. Three outputs are provided;
A greater than B (O
A > B
), A less than B (O
A < B
) and
A equal to B (O
A = B
). Three expander inputs (I
A > B
,
I
A < B
and I
A = B
) allow cascading of the devices without
external gates.
For proper compare operation the expander inputs to the
least significant position must be connected as follows:
I
A = B
= I
A > B
= HIGH, I
A < B
= LOW. For words greater than
4-bits, units can be cascaded by connecting outputs
O
A < B
and O
A = B
to the corresponding inputs of the next
significant comparator (input I
A > B
is connected to a
HIGH).
Operation is not restricted to binary codes, the devices will
work with any monotonic code. The function table
describes the operation of the device under all possible
logic conditions.
Fig.1 Functional diagram.
PINNING
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF4585BP(N):
16-lead DIL; plastic (SOT38-1)
HEF4585BD(F):
16-lead DIL; ceramic (cerdip) (SOT74)
HEF4585BT(D):
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
A
0
to A
3
word A parallel inputs
B
0
to B
3
word B parallel inputs
I
A > B
, I
A
<
B
, I
A = B
expander inputs
O
A > B
A greater than B output
O
A < B
A less than B output
O
A = B
A equal to B output
Fig.2 Pinning diagram.
January 1995
4
Philips Semiconductors
Product specification
4-bit magnitude comparator
HEF4585B
MSI
FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
The upper 11 lines describe the normal operation under all conditions that will occur in a single device or in a serial
expansion scheme.
The lower 2 lines describe the operation under abnormal conditions on the cascading inputs. These conditions occur
when the parallel expansion technique is used.
COMPARING INPUTS
CASCADING INPUTS
OUTPUTS
A
3
, B
3
A
2
, B
2
A
1
, B
1
A
0
, B
0
I
A
>
B
I
A
<
B
I
A = B
O
A
>
B
O
A
<
B
O
A = B
A
3
> B
3
X
X
X
H
X
X
H
L
L
A
3
< B
3
X
X
X
X
X
X
L
H
L
A
3
= B
3
A
2
> B
2
X
X
H
X
X
H
L
L
A
3
= B
3
A
2
< B
2
X
X
X
X
X
L
H
L
A
3
= B
3
A
2
= B
2
A
1
> B
1
X
H
X
X
H
L
L
A
3
= B
3
A
2
= B
2
A
1
< B
1
X
X
X
X
L
H
L
A
3
= B
3
A
2
= B
2
A
1
= B
1
A
0
> B
0
H
X
X
H
L
L
A
3
= B
3
A
2
= B
2
A
1
= B
1
A
0
< B
0
X
X
X
L
H
L
A
3
= B
3
A
2
= B
2
A
1
= B
1
A
0
= B
0
X
L
H
L
L
H
A
3
= B
3
A
2
= B
2
A
1
= B
1
A
0
= B
0
H
L
L
H
L
L
A
3
= B
3
A
2
= B
2
A
1
= B
1
A
0
= B
0
X
H
L
L
H
L
A
3
= B
3
A
2
= B
2
A
1
= B
1
A
0
= B
0
X
H
H
L
H
H
A
3
= B
3
A
2
= B
2
A
1
= B
1
A
0
= B
0
L
L
L
L
L
L
January 1995
5
Philips Semiconductors
Product specification
4-bit magnitude comparator
HEF4585B
MSI
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
C; C
L
= 50 pF; input transition times
20 ns
APPLICATION INFORMATION
Some examples of applications for the HEF4585B are:
Process controllers.
Servo-motor control.
V
DD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
A
n
, B
n
O
n
5
160
320 ns
133 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
65
130 ns
54 ns
+
(0,23 ns/pF) C
L
15
45
90 ns
37 ns
+
(0,16 ns/pF) C
L
5
150
300 ns
123 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
60
120 ns
49 ns
+
(0,23 ns/pF) C
L
15
45
90 ns
37 ns
+
(0,16 ns/pF) C
L
I
n
O
n
5
110
220 ns
83 ns
+
(0,55 ns/pF) C
L
HIGH to LOW
10
t
PHL
45
90 ns
34 ns
+
(0,23 ns/pF) C
L
15
30
60 ns
22 ns
+
(0,16 ns/pF) C
L
5
120
240 ns
93 ns
+
(0,55 ns/pF) C
L
LOW to HIGH
10
t
PLH
50
100 ns
39 ns
+
(0,23 ns/pF) C
L
15
35
70 ns
27 ns
+
(0,16 ns/pF) C
L
Output transition times
5
60
120 ns
10 ns
+
(1,0 ns/pF) C
L
HIGH to LOW
10
t
THL
30
60 ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40 ns
6 ns
+
(0,28 ns/pF) C
L
5
60
120 ns
10 ns
+
(1,0 ns/pF) C
L
LOW to HIGH
10
t
TLH
30
60 ns
9 ns
+
(0,42 ns/pF) C
L
15
20
40 ns
6 ns
+
(0,28 ns/pF) C
L
V
DD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
1250 f
i
+
(f
o
C
L
)
V
DD
2
where
dissipation per
10
5500 f
i
+
(f
o
C
L
)
V
DD
2
f
i
= input freq. (MHz)
package (P)
15
15 000 f
i
+
(f
o
C
L
)
V
DD
2
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
PDF 
ZIP
