Philips
Semiconductors
74F579
8-bit bidirectional binary counter (3-State)
Product specification
IC15 Data Handbook
1992 May 04
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
2
1992 May 04
853-0377 06639
FEATURES
Fully synchronous operation
Multiplexed 3-State I/O ports for bus oriented applications
Built in cascading carry capability
U/D pin to control direction of counting
Separate pins for Master reset and Synchronous operation
Center power pins to reduce effects of package inductance
Count frequency 115MHz Typ
Supply current 100mA Typ
See 74F269 for 24-pin separate I/O port version
See 74F779 for 16-pin version
DESCRIPTION
The 74F579 is a fully synchronous 8-stage Up/Down Counter with
multiplexed 3-State I/O ports for bus-oriented applications. It
features a preset capability for programmable operation, carry
look-ahead for easy cascading and a U/D input to control the
direction of counting. All state changes, except for the case of
asynchronous reset, are initiated by the rising edge of the clock.
TC output is not recommended for use as a clock or asynchronous
reset due to the possibility of decoding spikes.
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
CP
I/O0
I/O1
I/O2
I/O3
GND
I/O4
I/O5
I/O6
I/O7
VCC
MR
SR
CEP
CET
TC
PE
CS
OE
U/D
SF01085
ORDERING INFORMATION
TYPE
TYPICAL f
MAX
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F579
115MHz
100mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
10%,
T
amb
= 0
C to +70
C
PKG DWG #
20-Pin Plastic DIP
N74F579N
SOT146-1
20-Pin Plastic SOL
N74F579D
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
I/O
Data Inputs
3.5/1.0
70
A/0.6mA
I/O
n
Data Outputs
150/40
3.0mA/24mA
PE
Parallel Enable input (active Low)
1.0/1.0
20
A/0.6mA
U/D
Up/Down count control input
1.0/1.0
20
A/0.6mA
MR
Master Reset input (active Low)
1.0/1.0
20
A/0.6mA
SR
Synchronous Reset input (active Low)
1.0/1.0
20
A/0.6mA
CEP
Count Enable Parallel input (active Low)
1.0/1.0
20
A/0.6mA
CET
Count Enable Trickle input (active Low)
1.0/1.0
20
A/0.6mA
CS
Chip Select input (active Low)
1.0/1.0
20
A/0.6mA
OE
Output Enable input (active Low)
1.0/1.0
20
A/0.6mA
CP
Clock input (active Rising Edge)
1.0/1.0
20
A/0.6mA
TC
Terminal Count Output (active Low)
50/33
1.0mA/20mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20
A in the High state and 0.6mA in the Low state.
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
3
LOGIC SYMBOL
13
V
CC
= Pin 16
GND = Pin 6
3
4
5
7
8
9
10
1
18
SF01086
CEP
I/O0
I/O1
I/O4
I/O5
I/O6
I/O7
CP
CS
MR
SR
U/D
I/O2
I/O3
PE
12
20
19
14
2
17
11
OE
CET
15
TC
LOGIC SYMBOL (IEEE/IEC)
SF01087
1
3
4
5
2
8
9
10
6
1,2,3,4,
5,6,7,8
18
u
1
EN3
2,5,7, +/C8
[1]
[2]
[4]
[8]
[16]
[32]
[64]
[128]
15
3,5,6,8 CT=256
3,4,6,8 CT=0
14
20
17
13
11
19
12
2,4,7
R9
CTR DIV 256
&
&
M2[LOAD]
R1
1
1
1
1
1
&
EN6
1
G7
M4[DOWN]
M5[UP]
1
1
FUNCTION TABLE
INPUTS
OPERATING MODE
MR
SR
CS
PE
CEP
CET
U/D
OE
CP
X
X
H
X
X
X
X
X
X
I/O0 to I/O7 in high impedance (PE disabled)
X
X
L
H
X
X
X
H
X
I/O0 to I/O7 in high impedance
X
X
L
H
X
X
X
L
X
Flip-flop output appears on I/On lines
L
X
X
X
X
X
X
X
X
Asynchronous reset for all flip-flops
H
L
X
X
X
X
X
X
Synchronous reset for all flip-flops
H
H
L
L
X
X
X
X
Parallel load all flip-flops
H
H
(not LL)
H
X
X
X
Hold
H
H
(not LL)
X
H
X
X
Hold (TC held High)
H
H
(not LL)
L
L
H
X
Count up
H
H
(not LL)
L
L
L
X
Count down
H
=
High voltage level
L
=
Low voltage level
X
=
Don't care
=
Low-to-High clock transition
(not LL)
=
CS and PE should never be Low voltage level at the same time.
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
4
LOGIC DIAGRAM
For pinouts refer to Package Pin Configurations
CP
DETAIL A
DETAIL A
DETAIL A
DETAIL A
DETAIL A
DETAIL A
DETAIL A
DETAIL A
CP
D
Q
CP
DETAIL A
DATA
LOAD
Q
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
OE
CET
TC
TOGGLE
Q
Q
MR
MR
CEP
SR
PE
CS
U/D
19
13
12
11
2
3
4
5
7
8
9
10
14
18
17
15
1
20
VCC=pin 16
GND=pin 6
SF01088
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
5
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
0.5 to +7.0
V
V
IN
Input voltage
0.5 to +7.0
V
I
IN
Input current
30 to +5
mA
V
O
Voltage applied to output in High output state
0.5 to +V
CC
V
I
O
Current applied to output in Low output state
TC
40
mA
I
O
Current applied to output in Low output state
I/O0
48
mA
T
amb
Operating free-air temperature range
0 to +70
C
T
stg
Storage temperature
65 to +150
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
IK
Input clamp current
18
mA
I
O
High level output current
TC
1
mA
I
OH
High-level output current
I/O
n
3
mA
I
O
Low level output current
TC
20
mA
I
OL
Low-level output current
I/O
n
24
mA
T
amb
Operating free-air temperature range
0
70
C
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
2
MAX
UNIT
TC
V
CC
= MIN,
V
MAX
I
O
= 1mA
10%V
CC
2.5
V
V
O
High level output voltage
TC
V
IL
= MAX,
V
IH
= MIN
I
OH
= 1mA
5%V
CC
2.7
3.4
V
V
OH
High-level output voltage
I/O
IH
(V
IL
= 0.0V,
V
IH
= 4 5V
I
O
= 3mA
10%V
CC
2.4
3.3
V
I/O
n
V
IH
= 4.5V
for MR, CP inputs)
I
OH
= 3mA
5%V
CC
2.7
3.3
V
V
O
Low level output voltage
V
CC
= MIN,
V
MAX
I
O
= MAX
10%V
CC
0.35
0.50
V
V
OL
Low-level output voltage
V
IL
= MAX,
V
IH
= MIN
I
OL
= MAX,
5%V
CC
0.35
0.50
V
V
IK
Input clamp voltage
V
CC
= MIN, I
I
= I
IK
0.73
1.2
V
I
Input current
I/O
n
V
CC
= MAX, V
I
= 5.5V
1
mA
I
I
at maximum input voltage
others
V
CC
= MAX, V
I
= 7.0V
100
A
I
IH
High-level input current
except
V
CC
= MAX, V
I
= 2.7V
20
A
I
IL
Low-level input current
I/O
n
V
CC
= MAX, V
I
= 0.5V
0.6
mA
I
OZH
+ I
IH
Off-state output current
High-level voltage applied
I/O
V
CC
= MAX, V
O
= 2.7V
70
A
I
OZL
+ I
IL
Off-state output current
Low-level voltage applied
I/O
n
V
CC
= MAX, V
O
= 0.5V
600
A
I
OS
Short-circuit output current
3
V
CC
= MAX
60
150
mA
I
CCH
95
135
mA
I
CC
Supply current (total)
I
CCL
V
CC
= MAX
105
145
mA
I
CCZ
105
150
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under Recommended Operating Conditions for the applicable
type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter test, I
OS
tests should be performed last.
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
7
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500
T
amb
= 0
C to +70
C
V
CC
= +5.0V
10%
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
f
MAX
Maximum clock frequency
Waveform 1
100
115
80
MHz
t
PLH
t
PHL
Propagation delay
CP to I/O
n
Waveform 1
5.0
5.0
7.5
7.5
10.5
10.5
4.5
5.0
11.5
11.5
ns
ns
t
PLH
t
PHL
Propagation delay
CP to TC
Waveform 1
5.5
5.5
7.5
7.5
10.0
10.0
5.0
5.0
11.0
11.0
ns
ns
t
PLH
t
PHL
Propagation delay
U/D to TC
Waveform 4
3.5
4.5
5.5
6.5
8.0
8.0
3.5
4.5
9.0
9.0
ns
ns
t
PLH
t
PHL
Propagation delay
CET to TC
Waveform 3
3.5
3.5
5.5
6.0
7.0
8.0
3.5
3.5
8.5
8.5
ns
ns
t
PHL
Propagation delay
MR to I/O
n
Waveform 2
5.0
7.0
9.0
5.0
10.0
ns
t
PLH
t
PHL
Propagation delay
MR to TC
Waveform 4
4.0
6.0
6.5
8.0
9.0
10.5
4.0
6.0
10.5
12.5
ns
ns
t
PZH
t
PZL
Output Enable time
CS to I/O
n
Waveform 6
Waveform 7
4.0
5.5
5.0
7.0
8.5
10.5
3.5
5.0
10.0
11.5
ns
ns
t
PHZ
t
PLZ
Output Disable time
CS to I/O
n
Waveform 6
Waveform 7
3.0
5.0
5.0
7.5
7.5
9.5
3.0
4.5
9.0
11.0
ns
ns
t
PZH
t
PZL
Output Enable time
PE to I/O
n
Waveform 6
Waveform 7
3.0
5.0
4.5
6.5
8.0
10.0
3.0
4.5
9.0
11.0
ns
ns
t
PHZ
t
PLZ
Output Disable time
PE to I/O
n
Waveform 6
Waveform 7
3.0
2.5
4.0
4.0
7.5
7.5
3.0
2.0
9.0
8.5
ns
ns
t
PZH
t
PZL
Output Disable time
OE to I/O
n
Waveform 6
Waveform 7
2.5
4.5
4.0
5.5
7.0
9.0
2.5
4.0
8.5
10.5
ns
ns
t
PHZ
t
PLZ
Output Enable time
OE to I/O
n
Waveform 6
Waveform 7
1.0
2.0
2.5
4.0
4.0
7.0
1.0
2.0
5.5
8.0
ns
ns
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
8
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500
T
amb
= 0
C to +70
C
V
CC
= +5.0V
10%
C
L
= 50pF, R
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
t
s
(H)
t
s
(L)
Setup time, High or Low
I/O
n
to CP
Waveform 5
3.0
3.0
4.0
4.0
ns
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
I/O
n
to CP
Waveform 5
0
0
0
0
ns
ns
t
s
(H)
t
s
(L)
Setup time, High or Low
U/D to CP
Waveform 5
8.0
8.0
9.0
9.0
ns
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
U/D to CP
Waveform 5
0
0
0
0
ns
ns
t
s
(H)
t
s
(L)
Setup time, High or Low
PE, SR or CS to CP
Waveform 5
9.5
9.5
10.0
10.0
ns
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
PE, SR or CS to CP
Waveform 5
0
0
0
0
ns
ns
t
s
(H)
t
s
(L)
Setup time, High or Low
CEP or CET to CP
Waveform 5
5.0
9.0
5.5
10.5
ns
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
CEP or CET to CP
Waveform 5
0
0
0
0
ns
ns
t
w
(H)
t
w
(L)
CP Pulse width, High or Low
Waveform 1
4.5
4.5
4.5
4.5
ns
ns
t
w
(L)
MR Pulse width, Low
Waveform 2
3.0
3.0
ns
t
rec
Recovery time, MR to CP
Waveform 2
4.0
4.5
ns
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
9
AC WAVEFORMS
NOTE: For all waveforms V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
M
t
PHL
t
PLH
V
M
V
M
V
M
CP
I/O
n
1/f
MAX
t
W
(H)
t
W
(L)
t
PLH
t
PHL
V
M
V
M
TC
SF01089
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width and Maximum Clock Frequency
V
M
V
M
V
M
V
M
t
PHL
MR
CP
I/O
n
t
W
(L)
t
rec
SF01090
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
V
M
V
M
V
M
V
M
t
PLH
t
PHL
CET
TC
SF01091
Waveform 3. Propagation Delay, CET Input to
Terminal Count Output
V
M
V
M
V
M
t
PLH
t
PHL
MR, U/D
TC
SF01092
Waveform 4. Propagation Delay, U/D and MR Inputs to
Terminal Count Output
CP
PE, CS,
U/D, SR,
I/O
n,
CEP,
CET
V
M
V
M
V
M
V
M
V
M
V
M
t
s
(H)
t
s
(L)
t
h
(L)
t
h
(L)
SF01093
Waveform 5. Setup and Hold Times
V
M
V
M
V
M
t
PHZ
t
PZH
PE, OE,
CS
I/O
n
V
OH
-0.3V
SF01094
Waveform 6. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
V
M
V
M
V
M
t
PLZ
t
PZL
V
OL
+0.3V
PE, OE,
CS
I/O
n
SF01095
Waveform 7. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
10
TEST CIRCUIT AND WAVEFORMS
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLH
t
THL
1MHz
500ns
2.5ns
2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test Circuit for 3-State Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC electrical characteristics for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
tTHL (tf
)
tTLH (tr
)
tTLH (tr
)
AMP (V)
amplitude
3.0V
1.5V
V
M
RL
7.0V
SF00777
TEST
SWITCH
t
PLZ
closed
t
PZL
closed
All other
open
SWITCH POSITION
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
11
DIP20:
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
12
SO20:
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
1992 May 04
13
NOTES
Philips Semiconductors
Product specification
74F579
8-bit bidirectional binary counter (3-State)
yyyy mmm dd
14
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Date of release: 10-98
Document order number:
9397-750-05142
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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