Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

FEATURES

8-bit I

C GPIO

Operating power supply voltage range of 2.3 V to 5.5 V

5 V tolerant I/Os

Polarity inversion register

Active low interrupt output

Low stand-by current

Noise filter on SCL/SDA inputs

No glitch on power-up

Internal power-on reset

8 I/O pins which default to 8 inputs

0 kHz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA

Offered in three different packages: SO16, TSSOP16, and
HVQFN16

DESCRIPTION

The PCA9534 is a16-pin CMOS device that provide 8 bits of
General Purpose parallel Input/Output (GPIO) expansion for
I

C/SMBus applications and was developed to enhance the Philips

family of I

C I/O expanders. The improvements include higher drive

capability, 5V I/O tolerance, lower supply current, individual I/O
configuration, 400 kHz clock frequency, and smaller packaging. I/O
expanders provide a simple solution when additional I/O is needed
for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc.

The PCA9534 consist of an 8-bit Configuration register (Input or
Output selection); 8-bit Input register, 8-bit Output register and an
8-bit Polarity inversion register (Active HIGH or Active LOW
operation). The system master can enable the I/Os as either inputs
or outputs by writing to the I/O configuration bits. The data for each
Input or Output is kept in the corresponding Input or Output register.
The polarity of the input port register can be inverted with the
Polarity Inversion Register. All registers can be read by the system
master. Although pin-to-pin and I

C address compatible with the

PCF8574 series, software changes are required due to the
enhancements and are discussed in

Application Note AN469.

The PCA9534 is identical to the PCA9554 except for the removal of
the internal I/O pull-up resistor which greatly reduces power
consumption when the I/Os are held LOW.

The PCA9534 open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine.

Three hardware pins (A0, A1, A2) vary the fixed I

C address and

allow up to eight devices to share the same I

C/SMBus.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

16-Pin Plastic SO (wide)

C to +85

PCA9534D

SOT162-1

16-Pin Plastic TSSOP

C to +85

PCA9534PW

PCA9534

SOT403-1

16-Pin Plastic HVQFN

C to +85

PCA9534BS

9534

SOT629-1

Standard packing quantities and other packing data are available at www.standardproducts.philips.com/packaging.
I

C is a trademark of Philips Semiconductors Corporation.

SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I

C patent.

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

PIN CONFIGURATION -- SO, TSSOP

su01410

I/O0

I/O1

I/O2

I/O3

SDA

SCL

INT

I/O7

I/O6

I/O5

I/O4

Figure 1. Pin configuration -- SO, TSSOP

PIN CONFIGURATION -- HVQFN

su01670

TOP VIEW

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

INT

I/O6

I/O7

SDA

SCL

Figure 2. Pin Configuration -- HVQFN

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

SO, TSSOP

HVQFN

SYMBOL

FUNCTION

Address input 0

Address input 1

Address input 2

I/O0 to I/O3

Supply ground

912

710

I/O4 to I/O7

INT

Interrupt output (open drain)

SCL

Serial clock line

SDA

Serial data line

Supply voltage

BLOCK DIAGRAM

POWER-ON

RESET

INPUT

FILTER

C/SMBUS

CONTROL

INPUT/

OUTPUT

PORTS

WRITE pulse

READ pulse

SCL

SDA

8-BIT

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

SU01783

NOTE: ALL I/Os ARE SET TO INPUTS AT RESET

INT

FILTER

PCA9534

Figure 3. Block diagram

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

REGISTERS
Command Byte

Command

Protocol

Function

Read byte

Input port register

Read/write byte

Output port register

Read/write byte

Polarity inversion register

Read/write byte

Configuration register

The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.

Register 0 Input Port Register

bit

default

This register is a read only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.

The default value `X' is determined by the externally applied logic
level.

Register 1 Output Port Register

bit

default

This register reflects the outgoing logic levels of the pins defined as
outputs by Register 3. Bit values in this register have no effect on
pins defined as inputs. Reads from this register return the value that
is in the flip-flop controlling the output selection, NOT the actual pin
value.

Register 2 Polarity Inversion Register

bit

default

This register allows the user to invert the polarity of the Input Port
Register data. If a bit in this register is set (written with `1'), the
corresponding Input Port data is inverted. If a bit in this register is
cleared (written with a `0'), the Input Port data polarity is retained.

Register 3 Configuration Register

bit

default

This register configures the directions of the I/O pins. If a bit in this
register is set, the corresponding port pin is enabled as an input with
high impedance output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At reset, the I/Os are
configured as inputs.

Power-on Reset

When power is applied to V

, an internal power-on reset holds the

PCA9534 in a reset condition until V

has reached V

POR

. At that

point, the reset condition is released and the PCA9534 registers and
state machine will initialize to their default states. Thereafter, V

must be lowered below 0.2 V to reset the device.

For a power reset cycle, V

must be lowered below 0.2 V and then

restored to the operating voltage.

Interrupt Output

The open-drain interrupt output is activated when one of the port
pins change state and the pin is configured as an input. The
interrupt is deactivated when the input returns to its previous state or
the input port register is read.

Note that changing an I/O from an output to an input may cause a
false interrupt to occur if the state of the pin does not match the
contents of the input port register.

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7

WRITE PULSE

DATA FROM

SHIFT REGISTER

WRITE

CONFIGURATION

PULSE

INPUT PORT

POLARITY

INVERSION

OUTPUT

PORT

DATA FROM

SHIFT REGISTER

DATA FROM

SHIFT REGISTER

WRITE

POLARITY

PULSE

CONFIGURATION

OUTPUT PORT
REGISTER DATA

INPUT PORT
REGISTER DATA

POLARITY
REGISTER DATA

READ PULSE

SU01784

TO INT

ESD PROTECTION DIODE

I/O0 TO I/O7

NOTE:

At Power-on Reset, all registers return to default values.

Figure 4. Simplified schematic of I/O0 to I/O7

I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input. The input voltage may be raised
above V

to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is enabled,
depending on the state of the output port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance paths that exist between the
pin and either V

or V

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

Device address

SLAVE ADDRESS

su01685

FIXED

HARDWARE SELECTABLE

R/W

Figure 5. PCA9534 address

Bus transactions

Data is transmitted to the PCA9534 registers using the write mode as shown in Figures 6 and 7. Data is read from the PCA9534 registers using
the read mode as shown in Figures 8 and 9. These devices do not implement an auto-increment function so once a command byte has been
sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent.

SCL

WRITE TO

PORT

DATA OUT

FROM PORT

SDA

DATA 1

slave address

data to port

start condition

R/W

acknowledge
from slave

DATA 1 VALID

su01421

command byte

Figure 6. WRITE to output port register

SCL

SDA

DATA

slave address

data to register

start condition

R/W

acknowledge
from slave

su01422

command byte

1/0

DATA TO

Figure 7. WRITE to configuration or polarity inversion registers

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

A1 A0

COMMAND BYTE

acknowledge
from slave

R/W

acknowledge
from slave

acknowledge
from master

DATA

R/W

first byte

at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter

last byte

su01424

no acknowledge
from master

slave address

data from register

slave address

Figure 8. READ from register

READ FROM

PORT

DATA INTO

PORT

SDA

DATA 1

DATA 4

slave address

data from port

start condition

R/W

acknowledge
from slave

acknowledge
from master

stop
condition

DATA 4

DATA 2

DATA 3

su01465

no acknowledge
from master

INT

SCL

NOTES:
1. This figure assumes the command byte has previously been programmed with 00h.
2. Transfer of data can be stopped at any moment by a stop condition.

Figure 9. READ input port register

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

TYPICAL APPLICATION

SW2093

I/O

SCL

SDA

INT

RESET

MASTER

CONTROLLER

GND

PCA9534

SUBSYSTEM 3

(e.g. alarm

system)

SUBSYSTEM 2

(e.g. counter)

INT

ALARM

Controlled Switch
(e.g. CBT device)

ENABLE

10 k

2 k

NOTE: Device address configured as 0100100 for this example

I/O

, I/O

, configured as outputs

I/O

, I/O

, configured as inputs

I/O

, I/O

, are not used and have to be configured as outputs

10 k

INT

(5 V)

100 k

(

Figure 10. Typical application

Minimizing I

when the I/O is used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to V

through a resistor as shown in Figure 10. Since the LED acts as a

diode, when the LED is off the I/O V

is about 1.2 V less than V

. The supply current, I

, increases as V

becomes lower than V

and is

specified as

in the DC characteristics table.

Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or
equal to V

when the LED is off. Figure 11 shows a high value resistor in parallel with the LED. Figure 12 shows V

less than the LED supply

voltage by at least 1.2 V. Both of these methods maintain the I/O V

at or above V

and prevents additional supply current consumption when

the LED is off.

LEDx

LED

100 k

SW02086

Figure 11. High value resistor in parallel with the LED

3.3 V

LEDx

LED

SW02087

5 V

Figure 12. Device supplied by a lower voltage

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under "

Handling MOS devices".

DC CHARACTERISTICS

= 2.3 V to 5.5 V; V

= 0 V; T

amb

= 40

C to +85

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supplies

Supply voltage

2.3

5.5

Supply current

Operating mode; V

= 5.5 V; no load;

SCL

= 100 kHz

104

175

stbl

Standby current

Standby mode; V

= 5.5 V; no load;

= V

; f

SCL

= 0 kHz; I/O = inputs

0.25

stbh

Standby current

Standby mode; V

= 5.5 V; no load;

= V

; f

SCL

= 0 kHz; I/O = inputs

0.25

POR

Power-on reset voltage (Note 1)

No load; V

= V

or V

1.5

1.65

Input SCL; input/output SDA

LOW-level input voltage

0.5

0.3V

HIGH-level input voltage

0.7V

5.5

LOW-level output current

= 0.4 V

Leakage current

= V

Input capacitance

= V

I/Os

LOW-level input voltage

0.5

0.8

HIGH-level input voltage

2.0

5.5

= 0.5 V; V

= 2.3 V; Note 2

= 0.7 V; V

= 2.3 V; Note 2

LOW level output current

= 0.5 V; V

= 4.5 V; Note 2

LOW-level output current

= 0.7 V; V

= 4.5 V; Note 2

= 0.5 V; V

= 3.0 V; Note 2

= 0.7 V; V

= 3.0 V; Note 2

= 8 mA; V

= 2.3 V; Note 3

1.8

= 10 mA; V

= 2.3 V; Note 3

1.7

HIGH level output voltage

= 8 mA; V

= 3.0 V; Note 3

2.6

HIGH-level output voltage

= 10 mA; V

= 3.0 V; Note 3

2.5

= 8 mA; V

= 4.5 V; Note 3

4.1

= 10 mA; V

= 4.5 V; Note 3

4.0

Input leakage current

= V

Input capacitance

Interrupt INT

LOW-level output current

= 0.4 V

Select Inputs A0, A1, A2

LOW-level input voltage

0.5

0.8

HIGH-level input voltage

2.0

5.5

Input leakage current

NOTES:
1. V

must be lowered to 0.2 V in order to reset part.

2. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
3. The total current sourced by all I/Os must be limited to 85 mA.

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

BUF

HD;STA

LOW

HD;DAT

HIGH

SU;DAT

SU;STA

HD;STA

SU;STO

SDA

SCL

SU00645

Figure 13. Definition of timing

AC SPECIFICATIONS

SYMBOL

PARAMETER

STANDARD MODE

C-bus

FAST MODE

C-bus

UNITS

MIN

MAX

MIN

MAX

SCL

Operating frequency

100

400

kHz

BUF

Bus free time between STOP and START conditions

4.7

1.3

HD;STA

Hold time after (repeated) START condition

4.0

0.6

SU;STA

Repeated START condition setup time

4.7

0.6

SU;STO

Setup time for STOP condition

4.0

0.6

HD;DAT

Data in hold time

VD;ACK

Valid time for ACK condition

0.3

3.45

0.1

0.9

VD;DAT

Data out valid time

300

SU;DAT

Data setup time

250

100

LOW

Clock LOW period

4.7

1.3

HIGH

Clock HIGH period

4.0

0.6

Clock/Data fall time

300

20 + 0.1 C

300

Clock/Data rise time

1000

20 + 0.1 C

300

Pulse width of spikes that must be suppressed by the
input filters

Port Timing

Output data valid

200

Input data setup time

100

Input data hold time

Interrupt Timing

Interrupt valid

Interrupt reset

NOTES:
1. C

= total capacitance of one bus line in pF.

2. t

VD;ACK

= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

3. t

VD;DAT

= minimum time for SDA data out to be valid following SCL LOW.

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

PROTOCOL

SCL

SDA

HD;STA

SU;DAT

HD;DAT

VD;DAT

BUF

SU;STA

LOW

HIGH

1 / f

SCL

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

ACKNOWLEDGE

(A)

VD;ACK

SW02287

BIT 8

(R/W)

STOP

CONDITION

(S)

SU;STO

Figure 14. I

C-bus timing diagram; rise and fall times refer to V

and V

PULSE

GENERATOR

50 pF

DEFINITIONS

Load resistor.

Load capacitance includes jig and probe capacitance

Termination resistance should be equal to the output
impedance Z

of the pulse generators.

6.0 V

Open

D.U.T.

= 500

SW02142

Figure 15. Test circuitry for switching times

= 50 pF

500

Load Circuit

TEST

2 V

SA00652

500

From Output
Under Test

Open

GND

Figure 16. Test circuit

Philips Semiconductors

Product data sheet

PCA9534

8-bit I

C and SMBus low power I/O port with interrupt

2004 Sep 30

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2004

Date of release: 09-04

Document number:

9397 750 13506

Philips
Semiconductors

Data sheet status

[1]

Objective data

Preliminary data

Product data

Product
status

[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III

Document Outline

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Document Outline

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