Document Outline
- CONTENTS
- 1 FEATURES
- 2 GENERAL DESCRIPTION
- 3 ORDERING INFORMATION
- 4 BLOCK DIAGRAM
- 5 PINNING
- 6 FUNCTIONAL DESCRIPTION
- 6.1 Power-on reset
- 6.2 LCD bias generator
- 6.3 LCD voltage selector
- 6.4 LCD drive mode waveforms
- 6.5 Oscillator
- 6.5.1 Internal clock
- 6.5.2 External clock
- 6.6 Timing
- 6.7 Display latch
- 6.8 Shift register
- 6.9 Segment outputs
- 6.10 Backplane outputs
- 6.11 Display RAM
- 6.12 Data pointer
- 6.13 Subaddress counter
- 6.14 Output bank selector
- 6.15 Input bank selector
- 6.16 Blinker
- 21 PURCHASE OF PHILIPS I 2 C COMPONENTS
- 7 CHARACTERISTICS OF THE I 2 C-BUS
- 7.1 Bit transfer (see Fig.12)
- 7.2 START and STOP conditions (see Fig.13)
- 7.3 System configuration (see Fig.14)
- 7.4 Acknowledge (see Fig.15)
- 7.5 PCF8576 I 2 C-bus controller
- 7.6 Input filters
- 7.7 I 2 C-bus protocol
- 7.8 Command decoder
- 7.9 Display controller
- 7.10 Cascaded operation
- 8 LIMITING VALUES
- 9 HANDLING
- 10 DC CHARACTERISTICS
- 11 AC CHARACTERISTICS
- 11.1 Typical supply current characteristics
- 11.2 Typical characteristics of LCD outputs
- 12 APPLICATION INFORMATION
- 12.1 Chip-on-glass cascadability in single plane
- 13 BONDING PAD INFORMATION
- 14 TRAY INFORMATION: PCF8576U
- 15 TRAY INFORMATION: PCF8576U/2
- 16 PACKAGE OUTLINES
- 17 SOLDERING
- 17.1 Introduction to soldering surface mount packages
- 17.2 Reflow soldering
- 17.3 Wave soldering
- 17.4 Manual soldering
- 17.5 Suitability of surface mount IC packages for wave and reflow soldering methods
- 18 DATA SHEET STATUS
- 19 DEFINITIONS
- 20 DISCLAIMERS
DATA SHEET
Product specification
Supersedes data of 1998 Feb 06
File under Integrated Circuits, IC12
2001 Oct 02
INTEGRATED CIRCUITS
PCF8576
Universal LCD driver for low
multiplex rates
2001 Oct 02
2
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
BLOCK DIAGRAM
5
PINNING
6
FUNCTIONAL DESCRIPTION
6.1
Power-on reset
6.2
LCD bias generator
6.3
LCD voltage selector
6.4
LCD drive mode waveforms
6.5
Oscillator
6.5.1
Internal clock
6.5.2
External clock
6.6
Timing
6.7
Display latch
6.8
Shift register
6.9
Segment outputs
6.10
Backplane outputs
6.11
Display RAM
6.12
Data pointer
6.13
Subaddress counter
6.14
Output bank selector
6.15
Input bank selector
6.16
Blinker
7
CHARACTERISTICS OF THE I
2
C-BUS
7.1
Bit transfer (see Fig.12)
7.2
START and STOP conditions (see Fig.13)
7.3
System configuration (see Fig.14)
7.4
Acknowledge (see Fig.15)
7.5
PCF8576 I
2
C-bus controller
7.6
Input filters
7.7
I
2
C-bus protocol
7.8
Command decoder
7.9
Display controller
7.10
Cascaded operation
8
LIMITING VALUES
9
HANDLING
10
DC CHARACTERISTICS
11
AC CHARACTERISTICS
11.1
Typical supply current characteristics
11.2
Typical characteristics of LCD outputs
12
APPLICATION INFORMATION
12.1
Chip-on-glass cascadability in single plane
13
BONDING PAD INFORMATION
14
TRAY INFORMATION: PCF8576U
15
TRAY INFORMATION: PCF8576U/2
16
PACKAGE OUTLINES
17
SOLDERING
17.1
Introduction to soldering surface mount
packages
17.2
Reflow soldering
17.3
Wave soldering
17.4
Manual soldering
17.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
18
DATA SHEET STATUS
19
DEFINITIONS
20
DISCLAIMERS
21
PURCHASE OF PHILIPS I
2
C COMPONENTS
2001 Oct 02
3
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
1
FEATURES
Single-chip LCD controller/driver
Selectable backplane drive configuration: static or 2/3/4
backplane multiplexing
Selectable display bias configuration: static,
1
/
2
or
1
/
3
Internal LCD bias generation with voltage-follower
buffers
40 segment drives: up to twenty 8-segment numeric
characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements
40
4-bit RAM for display data storage
Auto-incremented display data loading across device
subaddress boundaries
Display memory bank switching in static and duplex
drive modes
Versatile blinking modes
LCD and logic supplies may be separated
Wide power supply range: from 2 V for low-threshold
LCDs and up to 9 V for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs
Low power consumption
Power-saving mode for extremely low power
consumption in battery-operated and telephone
applications
I
2
C-bus interface
TTL/CMOS compatible
Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
May be cascaded for large LCD applications (up to
2560 segments possible)
Cascadable with 24-segment LCD driver PCF8566
Optimized pinning for plane wiring in both single and
multiple PCF8576 applications
Space-saving 56-lead plastic very small outline package
(VSO56)
Very low external component count (at most one
resistor, even in multiple device applications)
Compatible with chip-on-glass technology
Manufactured in silicon gate CMOS process.
2
GENERAL DESCRIPTION
The PCF8576 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments and can easily be cascaded for larger LCD
applications. The PCF8576 is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I
2
C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
3
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
PCF8576T
VSO56
plastic very small outline package; 56 leads
SOT190-1
PCF8576U
-
chip in tray
-
PCF8576U/2
-
chip with bumps in tray
-
PCF8576U/5
-
unsawn wafer
-
PCF8576U/10
FFC
chip on film frame carrier (FFC)
-
PCF8576U/12
FFC
chip with bumps on film frame carrier (FFC)
-
2001
Oct
02
4
Philips Semiconductors
Product specification
Univ
ersal
LCD
dr
iv
er
f
o
r
l
o
w
m
ultiple
x
r
ates
PCF8576
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4
BLOCK DIA
GRAM
handbook, full pagewidth
MBK276
LCD
VOLTAGE
SELECTOR
VLCD
12
VDD
5
R
R
R
TIMING
BLINKER
OSCILLATOR
INPUT
FILTERS
I C - BUS
CONTROLLER
2
POWER-
ON
RESET
CLK
4
SYNC
3
OSC
6
VSS
11
SCL
2
SDA
1
SA0
10
DISPLAY
CONTROLLER
COMMAND
DECODER
BACKPLANE
OUTPUTS
13
BP0
14
BP2
15
BP1
16
BP3
INPUT
BANK
SELECTOR
DISPLAY
RAM
40 x 4 BITS
OUTPUT
BANK
SELECTOR
DATA
POINTER
SUB-
ADDRESS
COUNTER
DISPLAY SEGMENT OUTPUTS
DISPLAY LATCH
SHIFT REGISTER
17 to 56
S0 to S39
A0
7
A1
8
A2
9
PCF8576
LCD BIAS
GENERATOR
40
Fig.1 Block diagram (for VSO56 package; SOT190-1).
2001 Oct 02
5
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
5
PINNING
SYMBOL
PIN
DESCRIPTION
SDA
1
I
2
C-bus serial data input/output
SCL
2
I
2
C-bus serial clock input
SYNC
3
cascade synchronization input/output
CLK
4
external clock input/output
V
DD
5
supply voltage
OSC
6
oscillator input
A0 to A2
7 to 9
I
2
C-bus subaddress inputs
SA0
10
I
2
C-bus slave address input; bit 0
V
SS
11
logic ground
V
LCD
12
LCD supply voltage
BP0, BP2, BP1 and BP3
13 to 16
LCD backplane outputs
S0 to S39
17 to 56
LCD segment outputs
2001 Oct 02
6
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Fig.2 Pin configuration; SOT190-1.
handbook, halfpage
PCF8576T
MBK278
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SDA
SCL
SYNC
CLK
V
OSC
A0
A1
A2
SA0
V
V
BP0
BP2
BP1
BP3
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
DD
SS
LCD
2001 Oct 02
7
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
6
FUNCTIONAL DESCRIPTION
The PCF8576 is a versatile peripheral device designed to
interface to any microprocessor/microcontroller to a wide
variety of LCDs. It can directly drive any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments. The display configurations possible with
the PCF8576 depend on the number of active backplane
outputs required; a selection of display configurations is
given in Table .
All of the display configurations given in Table can be
implemented in the typical system shown in Fig.3.
The host microprocessor/microcontroller maintains the
2-line I
2
C-bus communication channel with the PCF8576.
The internal oscillator is selected by connecting pin OSC
to pin V
SS
. The appropriate biasing voltages for the
multiplexed LCD waveforms are generated internally. The
only other connections required to complete the system
are to the power supplies (V
DD
, V
SS
and V
LCD
) and the
LCD panel chosen for the application.
Selection of display configurations
NUMBER OF
7-SEGMENTS NUMERIC
14-SEGMENTS
ALPHANUMERIC
DOT MATRIX
BACKPLANES
SEGMENTS
DIGITS
INDICATOR
SYMBOLS
CHARACTERS
INDICATOR
SYMBOLS
4
160
20
20
10
20
160 dots (4
40)
3
120
15
15
8
8
120 dots (3
40)
2
80
10
10
5
10
80 dots (2
40)
1
40
5
5
2
12
40 dots (1
40)
Fig.3 Typical system configuration.
handbook, full pagewidth
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
R
tr
2CB
SDA
SCL
OSC
ROSC
1
17 to 56
13 to 16
2
6
7
8
5
12
9
10
11
40 segment drives
4 backplanes
LCD PANEL
(up to 160
elements)
PCF8576
A0
A1
A2
SS
SA0 V
SS
V
DD
V
DD
V
LCD
V
MBK277
2001 Oct 02
8
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
6.1
Power-on reset
At power-on the PCF8576 resets to a starting condition as
follows:
1. All backplane outputs are set to V
DD
.
2. All segment outputs are set to V
DD
.
3. The drive mode `1 : 4 multiplex with
1
/
3
bias' is selected.
4. Blinking is switched off.
5. Input and output bank selectors are reset (as defined
in Table 4).
6. The I
2
C-bus interface is initialized.
7. The data pointer and the subaddress counter are
cleared.
Data transfers on the I
2
C-bus should be avoided for 1 ms
following power-on to allow completion of the reset action.
6.2
LCD bias generator
The full-scale LCD voltage (V
op
) is obtained from
V
DD
-
V
LCD
. The LCD voltage may be temperature
compensated externally through the V
LCD
supply to pin 12.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of the three series resistors
connected between V
DD
and V
LCD
. The centre resistor can
be switched out of the circuit to provide a
1
/
2
bias voltage
level for the 1 : 2 multiplex configuration.
6.3
LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of V
op
= V
DD
-
V
LCD
and the
resulting discrimination ratios (D), are given in Table 1.
A practical value for V
op
is determined by equating V
off(rms)
with a defined LCD threshold voltage (V
th
), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is V
op
> 3V
th
approximately.
Multiplex drive ratios of 1 : 3 and 1 : 4 with
1
/
2
bias are
possible but the discrimination and hence the contrast
ratios are smaller (
= 1.732 for 1 : 3 multiplex or
= 1.528 for 1 : 4 multiplex).
The advantage of these modes is a reduction of the LCD
full-scale voltage V
op
as follows:
1 : 3 multiplex (
1
/
2
bias):
V
op
=
= 2.449 V
off(rms)
1 : 4 multiplex (
1
/
2
bias):
V
op
=
= 2.309 V
off(rms)
These compare with V
op
= 3 V
off(rms)
when
1
/
3
bias is used.
3
21
3
----------
6
V
off rms
4
3
(
)
3
----------------------
Table 1
Preferred LCD drive modes: summary of characteristics
LCD DRIVE MODE
NUMBER OF
LCD BIAS
CONFIGURATION
BACKPLANES
LEVELS
static
1
2
static
0
1
1 : 2
2
3
1
/
2
0.354
0.791
2.236
1 : 2
2
4
1
/
3
0.333
0.745
2.236
1 : 3
3
4
1
/
3
0.333
0.638
1.915
1 : 4
4
4
1
/
3
0.333
0.577
1.732
V
off(rms)
V
op
---------------------
V
on(rms)
V
op
---------------------
D
V
on(rms)
V
off(rms)
---------------------
=
2001 Oct 02
9
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
6.4
LCD drive mode waveforms
The static LCD drive mode is used when a single
backplane is provided in the LCD. Backplane and segment
drive waveforms for this mode are shown in Fig.4.
When two backplanes are provided in the LCD, the 1 : 2
multiplex mode applies. The PCF8576 allows use of
1
/
2
bias or
1
/
3
bias in this mode as shown in Figs 5 and 6.
When three backplanes are provided in the LCD, the 1 : 3
multiplex drive mode applies, as shown in Fig.7.
When four backplanes are provided in the LCD, the 1 : 4
multiplex drive mode applies, as shown in Fig.8.
V
state1
t
( )
V
S
n
t
( )
V
BP0
t
( )
=
V
on(rms)
V
op
=
V
state2
t
( )
V
S
n
1
+
t
( )
V
BP0
t
( )
=
V
off(rms)
0 V
=
Fig.4 Static drive mode waveforms (V
op
= V
DD
-
V
LCD
).
MBE539
V DD
V LCD
V LCD
V DD
V LCD
V op
Vop
state 1
0
BP0
Sn
S n 1
V op
Vop
state 2
0
(a) waveforms at driver
(b) resultant waveforms
at LCD segment
LCD segments
state 1
(on)
state 2
(off)
Tframe
VDD
2001 Oct 02
10
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Fig.5 Waveforms for the 1 : 2 multiplex drive mode with
1
/
2
bias (V
op
= V
DD
-
V
LCD
).
V
state1
t
( )
V
S
n
t
( )
V
BP0
t
( )
=
V
on(rms)
0.791V
op
=
V
state2
t
( )
V
S
n
t
( )
V
BP1
t
( )
=
V
off(rms)
0.354V
op
=
MBE540
V
(V
)/2
V
DD
V /2
op
Vop
state 1
0
BP0
S n 1
(a) waveforms at driver
(b) resultant waveforms
at LCD segment
LCD segments
state 2
Tframe
DD
LCD
VLCD
BP1
Sn
Vop
V /2
op
V /2
op
Vop
state 2
0
Vop
V /2
op
state 1
V
(V
)/2
V
DD
DD
LCD
VLCD
VLCD
VLCD
VDD
VDD
2001 Oct 02
11
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Fig.6 Waveforms for the 1 : 2 multiplex drive mode with
1
/
3
bias (V
op
= V
DD
-
V
LCD
).
V
state1
t
( )
V
S
n
t
( )
V
BP0
t
( )
=
V
on(rms)
0.745V
op
=
V
state2
t
( )
V
S
n
t
( )
V
BP1
t
( )
=
V
off(rms)
0.333V
op
=
MBE541
VDD
2V /3
op
Vop
state 1
0
BP0
S n 1
(a) waveforms at driver
(b) resultant waveforms
at LCD segment
LCD segments
state 2
Tframe
V V /3
DD
op
VLCD
BP1
Sn
Vop
state 1
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
V /3
op
2V /3
op
V /3
op
2V /3
op
Vop
state 2
0
Vop
V /3
op
2V /3
op
V /3
op
2001 Oct 02
12
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
MBE542
2V /3
op
Vop
state 1
0
BP0
(b) resultant waveforms
at LCD segment
LCD segments
state 2
Tframe
BP1
Vop
state 1
V /3
op
2V /3
op
V /3
op
2V /3
op
Vop
state 2
0
Vop
V /3
op
2V /3
op
V /3
op
Sn 1
Sn 2
(a) waveforms at driver
S n
BP2/S23
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
Fig.7 Waveforms for the 1 : 3 multiplex drive mode (V
op
= V
DD
-
V
LCD
).
V
state1
t
( )
V
S
n
t
( )
V
BP0
t
( )
=
V
on(rms)
0.638V
op
=
V
state2
t
( )
V
S
n
t
( )
V
BP1
t
( )
=
V
off(rms)
0.333V
op
=
2001 Oct 02
13
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Fig.8 Waveforms for the 1 : 4 multiplex drive mode (V
op
= V
DD
-
V
LCD
).
MBE543
2V /3
op
Vop
state 1
0
BP0
(b) resultant waveforms
at LCD segment
LCD segments
state 2
Tframe
BP1
Vop
state 1
V /3
op
2V /3
op
V /3
op
2V /3
op
Vop
state 2
0
Vop
V /3
op
2V /3
op
V /3
op
Sn 1
BP2
S n 2
Sn 3
(a) waveforms at driver
Sn
BP3
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
VDD
V V /3
DD
op
VLCD
V 2V /3
DD
op
V
state1
t
( )
V
S
n
t
( )
V
BP0
t
( )
=
V
on(rms)
0.577V
op
=
V
state2
t
( )
V
S
n
t
( )
V
BP1
t
( )
=
V
off(rms)
0.333V
op
=
2001 Oct 02
14
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
6.5
Oscillator
6.5.1
I
NTERNAL CLOCK
The internal logic and the LCD drive signals of the
PCF8576 are timed either by the internal oscillator or from
an external clock. When the internal oscillator is used,
pin OSC should be connected to pin V
SS
. In this event, the
output from pin CLK provides the clock signal for
cascaded PCF8566s in the system.
Where resistor R
osc
to V
SS
is present, the internal oscillator
is selected. The relationship between the oscillator
frequency on pin CLK (f
clk
) and R
osc
is shown in Fig.9.
6.5.2
E
XTERNAL CLOCK
The condition for external clock is made by connecting
pin OSC to pin V
DD
; pin CLK then becomes the external
clock input.
The clock frequency (f
clk
) determines the LCD frame
frequency and the maximum rate for data reception from
the I
2
C-bus. To allow I
2
C-bus transmissions at their
maximum data rate of 100 kHz, f
clk
should be chosen to be
above 125 kHz.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6
Timing
The timing of the PCF8576 organizes the internal data flow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal SYNC
maintains the correct timing relationship between the
PCF8576s in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 2). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to
pin CLK when external clock is used.
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power-saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation. The
lower clock frequency has the disadvantage of increasing
the response time when large amounts of display data are
transmitted on the I
2
C-bus.
When a device is unable to digest a display data byte
before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I
2
C-bus but no data loss occurs.
Table 2
LCD frame frequencies
6.7
Display latch
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
6.8
Shift register
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.
Fig.9 Oscillator frequency as a function of R
osc
.
f
clk
3.4
10
7
R
osc
------------------------
kHz
(
)
10
4
MBE531
10
3
10
2
10
10
3
10
2
f
clk
(kHz)
R
(k
)
osc
min
max
PCF8576 MODE
FRAME
FREQUENCY
NOMINAL
FRAME
FREQUENCY
(Hz)
Normal mode
64
Power-saving mode
64
f
clk
2880
-------------
f
clk
480
----------
2001 Oct 02
15
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
6.9
Segment outputs
The LCD drive section includes 40 segment outputs
pins S0 to S39 which should be connected directly to the
LCD. The segment output signals are generated in
accordance with the multiplexed backplane signals and
with data resident in the display latch. When less than
40 segment outputs are required the unused segment
outputs should be left open-circuit.
6.10
Backplane outputs
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be connected together to give
enhanced drive capabilities. In the 1 : 2 multiplex drive
mode BP0 and BP2, BP1 and BP3 respectively carry the
same signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
6.11
Display RAM
The display RAM is a static 40
4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the on
state of the corresponding LCD segment; similarly, a
logic 0 indicates the off state. There is a one-to-one
correspondence between the RAM addresses and the
segment outputs, and between the individual bits of a RAM
word and the backplane outputs. The first RAM column
corresponds to the 40 segments operated with respect to
backplane BP0 (see Fig.10). In multiplexed LCD
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.
When display data is transmitted to the PCF8576 the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode. To
illustrate the filling order, an example of a 7-segment
numeric display showing all drive modes is given in Fig.11;
the RAM filling organization depicted applies equally to
other LCD types.
With reference to Fig.11, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 multiplex drive mode
the eight transmitted data bits are placed in bits 0 and 1 of
four successive display RAM addresses. In the 1 : 3
multiplex drive mode these bits are placed in
bits 0, 1 and 2 of three successive addresses, with bit 2 of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because full bytes are always transmitted. In
the 1 : 4 multiplex drive mode the eight transmitted data
bits are placed in bits 0, 1, 2 and 3 of two successive
display RAM addresses.
Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.
0
0
1
2
3
1
2
3
4
35
36
37
38
39
display RAM addresses (rows) / segment outputs (S)
display RAM bits
(columns) /
backplane outputs
(BP)
MBE525
2001 Oct 02
16
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
6.12
Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an
arriving data byte is stored starting at the display RAM
address indicated by the data pointer thereby observing
the filling order shown in Fig.11. The data pointer is
automatically incremented in accordance with the chosen
LCD configuration. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode) or
by two (1 : 4 multiplex drive mode).
6.13
Subaddress counter
The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to A0, A1
and A2. The subaddress counter value is defined by the
DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place. The
subaddress counter is also incremented when the data
pointer overflows.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576 occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1 : 3 multiplex mode).
6.14
Output bank selector
This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence. In 1 : 4
multiplex, all RAM addresses of bit 0 are the first to be
selected, these are followed by the contents of bit 1, bit 2
and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2
are selected sequentially. In 1 : 2 multiplex, bits 0 and 1
are selected and, in the static mode, bit 0 is selected.
The PCF8576 includes a RAM bank switching feature in
the static and 1 : 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1 : 2 drive mode, the contents of
bits 2 and 3 may be selected instead of bits 0 and 1. This
gives the provision for preparing display information in an
alternative bank and to be able to switch to it once it is
assembled.
6.15
Input bank selector
The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. Display data can be loaded in bit 2 in static
drive mode or in bits 2 and 3 in 1 : 2 drive mode by using
the BANK SELECT command. The input bank selector
functions independent of the output bank selector.
2001 Oct 02
17
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
6.16
Blinker
The display blinking capabilities of the PCF8576 are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table 3.
An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and
1 : 2 LCD drive modes and can be implemented without
any communication overheads. By means of the output
bank selector, the displayed RAM banks are exchanged
with alternate RAM banks at the blinking frequency. This
mode can also be specified by the BLINK command.
In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E
at the required rate using the MODE SET command.
Table 3
Blinking frequencies
BLINKING MODE
NORMAL OPERATING
MODE RATIO
POWER-SAVING MODE
RATIO
NOMINAL BLINKING
FREQUENCY
Off
-
-
blinking off
2 Hz
2 Hz
1 Hz
1 Hz
0.5 Hz
0.5 Hz
f
clk
92160
----------------
f
clk
15360
----------------
f
clk
184320
--------------------
f
clk
30720
----------------
f
clk
368640
--------------------
f
clk
61440
----------------
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2001
Oct
02
18
Philips Semiconductors
Product specification
Univ
ersal
LCD
dr
iv
er
f
o
r
l
o
w
m
ultiple
x
r
ates
PCF8576
handbook, full pagewidth
MBK389
S
2
n
S
1
n
S
7
n
S
n
S
n
S
3
n
S
5
n
S
2
n
S
3
n
S
1
n
S
1
n
S
1
n
S
2
n
S
n
S
6
n
S
n
S
4
n
DP
DP
DP
DP
a
f
b
g
e
c
d
a
f
b
g
e
c
d
a
f
b
g
e
c
d
a
f
b
g
e
c
d
BP0
BP0
BP0
BP1
BP1
BP2
BP1
BP2
BP3
BP0
n
c
x
x
x
0
1
2
3
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
n 1
n 2
n 3
n 4
n 5
n 6
n 7
bit/
BP
n
a
b
x
x
0
1
2
3
f
g
x
x
e
c
x
x
d
DP
x
x
n 1
n 2
n 3
bit/
BP
n
b
DP
c
x
0
1
2
3
a
d
g
x
f
e
x
x
n 1
n 2
bit/
BP
n
a
c
b
DP
0
1
2
3
f
e
g
d
n 1
bit/
BP
c b a f
g e d DP
a b f
g e c d DP
b DP c a d g f
e
a c
b DP f
e g d
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
drive mode
static
1 : 2
multiplex
1 : 3
multiplex
1 : 4
multiplex
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
x = data bit unchanged.
Fig.11 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I
2
C-bus.
2001 Oct 02
19
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
7
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
7.1
Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as a control signal.
7.2
START and STOP conditions (see Fig.13)
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is
HIGH is defined as the STOP condition (P).
7.3
System configuration (see Fig.14)
A device generating a message is a `transmitter', a device
receiving a message is the `receiver'. The device that
controls the message is the `master' and the devices which
are controlled by the master are the `slaves'.
7.4
Acknowledge (see Fig.15)
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
7.5
PCF8576 I
2
C-bus controller
The PCF8576 acts as an I
2
C-bus slave receiver. It does
not initiate I
2
C-bus transfers or transmit data to an I
2
C-bus
master receiver. The only data output from the PCF8576
are the acknowledge signals of the selected devices.
Device selection depends on the I
2
C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device application, the hardware subaddress
inputs A0, A1 and A2 are normally connected to V
SS
which
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are connected to V
SS
or V
DD
in
accordance with a binary coding scheme such that no two
devices with a common I
2
C-bus slave address have the
same hardware subaddress.
In the power-saving mode it is possible that the PCF8576
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8576 forces the SCL line to LOW
until its internal operations are completed. This is known
as the `clock synchronization feature' of the I
2
C-bus and
serves to slow down fast transmitters. Data loss does not
occur.
7.6
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.7
I
2
C-bus protocol
Two I
2
C-bus slave addresses (0111000 and 0111001) are
reserved for the PCF8576. The least significant bit of the
slave address that a PCF8576 will respond to is defined by
the level connected at its input pin SA0. Therefore, two
types of PCF8576 can be distinguished on the same
I
2
C-bus which allows:
Up to 16 PCF8576s on the same I
2
C-bus for very large
LCD applications
The use of two types of LCD multiplex on the same
I
2
C-bus.
The I
2
C-bus protocol is shown in Fig.16. The sequence is
initiated with a START condition (S) from the I
2
C-bus
master which is followed by one of the two PCF8576 slave
addresses available. All PCF8576s with the corresponding
SA0 level acknowledge in parallel with the slave address
but all PCF8576s with the alternative SA0 level ignore the
whole I
2
C-bus transfer.
2001 Oct 02
20
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
After acknowledgement, one or more command bytes (m)
follow which define the status of the addressed PCF8576s.
The last command byte is tagged with a cleared most
significant bit, the continuation bit C. The command bytes
are also acknowledged by all addressed PCF8576s on the
bus.
After the last command byte, a series of display data bytes
(n) may follow. These display bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data is directed to the intended PCF8576 device. The
acknowledgement after each byte is made only by the (A0,
A1 and A2) addressed PCF8576. After the last display
byte, the I
2
C-bus master issues a STOP condition (P).
7.8
Command decoder
The command decoder identifies command bytes that
arrive on the I
2
C-bus. All available commands carry a
continuation bit C in their most significant bit position
(Fig.17). When this bit is set, it indicates that the next byte
of the transfer to arrive will also represent a command. If
this bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8576 are defined
in Table 4.
Fig.12 Bit transfer.
MBA607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.13 Definition of START and STOP conditions.
handbook, full pagewidth
MBC622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
2001 Oct 02
21
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Fig.14 System configuration.
MGA807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig.15 Acknowledgement on the I
2
C-bus.
handbook, full pagewidth
MBC602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
2001 Oct 02
22
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Fig.16 I
2
C-bus protocol.
handbook, full pagewidth
MBK279
S
A
0
S
0 1 1 1 0 0
0 A C
COMMAND
A
P
A
DISPLAY DATA
slave address
/
R W
acknowledge by
all addressed
PCF8576s
acknowledge
by A0, A1 and A2
selected
PCF8576 only
n 0 byte(s)
n 1 byte(s)
1 byte
update data pointers
and if necessary,
subaddress counter
Fig.17 General format of command byte.
C = 0; last command.
C = 1; commands continue.
MSA833
REST OF OPCODE
C
MSB
LSB
2001 Oct 02
23
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Table 4
Definition of PCF8576 commands
COMMAND
OPCODE
OPTIONS
DESCRIPTION
MODE SET
C 1
0
LP
E
B
M1
M0
Table 5
Defines LCD drive mode.
Table 6
Defines LCD bias configuration.
Table 7
Defines display status. The possibility to disable the
display allows implementation of blinking under
external control.
Table 8
Defines power dissipation mode.
LOAD DATA
POINTER
C 0 P5 P4 P3 P2
P1
P0
Table 9
Six bits of immediate data, bits P5 to P0, are
transferred to the data pointer to define one of forty
display RAM addresses.
DEVICE
SELECT
C 1
1
0
0
A2
A1
A0
Table 10
Three bits of immediate data, bits A2 to A0, are
transferred to the subaddress counter to define one of
eight hardware subaddresses.
BANK
SELECT
C 1
1
1
1
0
I
O
Table 11
Defines input bank selection (storage of arriving
display data).
Table 12
Defines output bank selection (retrieval of LCD display
data). The BANK SELECT command has no effect in
1 : 3 and 1 : 4 multiplex drive modes.
BLINK
C 1
1
1
0
A
BF1 BF0
Table 13
Defines the blinking frequency.
Table 14
Selects the blinking mode; normal operation with
frequency set by BF1, BF0 or blinking by alternation of
display RAM banks. Alternation blinking does not
apply in 1 : 3 and 1 : 4 multiplex drive modes.
Table 5
MODE SET option 1
Table 6
MODE SET option 2
Table 7
MODE SET option 3
Table 8
MODE SET option 4
Table 9
LOAD DATA POINTER option 1
Table 10 DEVICE SELECT option 1
Table 11 BANK SELECT option 1
LCD DRIVE MODE
BITS
DRIVE MODE
BACKPLANE
M1
M0
Static
1 BP
0
1
1 : 2
MUX (2 BP)
1
0
1 : 3
MUX (3 BP)
1
1
1 : 4
MUX (4 BP)
0
0
LCD BIAS
BIT B
1
/
3
bias
0
1
/
2
bias
1
DISPLAY STATUS
BIT E
Disabled (blank)
0
Enabled
1
MODE
BIT LP
Normal mode
0
Power-saving mode
1
DESCRIPTION
BITS
6-bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0
DESCRIPTION
BITS
3-bit binary value of 0 to 7
A2
A1
A0
STATIC
1 : 2 MUX
BIT I
RAM bit 0
RAM bits 0 and 1
0
RAM bit 2
RAM bits 2 and 3
1
2001 Oct 02
24
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Table 12 BANK SELECT option 2
Table 13 BLINK option 1
Table 14 BLINK option 2
7.9
Display controller
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8576 and co-ordinates their effects. The
controller is also responsible for loading display data into
the display RAM as required by the filling order.
STATIC
1 : 2 MUX
BIT O
RAM bit 0
RAM bits 0 and 1
0
RAM bit 2
RAM bits 2 and 3
1
BLINK FREQUENCY
BITS
BF1
BF0
Off
0
0
2 Hz
0
1
1 Hz
1
0
0.5 Hz
1
1
BLINK MODE
BIT A
Normal blinking
0
Alternation blinking
1
7.10
Cascaded operation
In large display configurations, up to 16 PCF8576s can be
distinguished on the same I
2
C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
programmable I
2
C-bus slave address (SA0). When
cascaded PCF8576s are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8576s of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (see Fig.18).
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8576s. This
synchronization is guaranteed after the Power-on reset.
The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8576s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output selection being realized as an open-drain driver
with an internal pull-up resistor. A PCF8576 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times. Should
synchronization in the cascade be lost, it will be restored
by the first PCF8576 to assert SYNC. The timing
relationship between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.19.
For single plane wiring of packaged PCF8576s and
chip-on-glass cascading, see Chapter 12.
2001 Oct 02
25
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Fig.18 Cascaded PCF8576 configuration.
handbook, full pagewidth
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
CLK
OSC
SYNC
1
17 to 56
2
3
4
6
7
8
5
12
9
10
11
7
8
9
10
11
40 segment drives
4 backplanes
40 segment drives
LCD PANEL
(up to 2560
elements)
PCF8576
A0
A1
A2
SS
SA0 V
SS
V
DD
V
LCD
V
DD
V
LCD
V
MBK280
SDA
SCL
SYNC
CLK
OSC
1
5
12
2
3
4
6
17 to 56
13, 15
14, 16
13, 15
14, 16
BP0 to BP3
(open-circuit)
A0
A1
A2
SA0 VSS
VDD
VLCD
PCF8576
BP0 to BP3
R
tr
2CB
2001 Oct 02
26
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Fig.19 Synchronization of the cascade for the various PCF8576 drive modes.
Excessive capacitive coupling between SCL or CLK and SYNC may cause erroneous synchronization. If this proves to be a problem, the capacitance
of the SYNC line should be increased (e.g. by an external capacitor between SYNC and V
DD
). Degradation of the positive edge of the SYNC pulse may
be countered by an external pull-up resistor.
handbook, full pagewidth
T
=
frame
f
frame
1
BP0
SYNC
BP1
(1/2 bias)
SYNC
BP2
(a) static drive mode.
(b) 1 : 2 multiplex drive mode.
(c) 1 : 3 multiplex drive mode.
(d) 1 : 4 multiplex drive mode.
BP3
SYNC
SYNC
BP1
(1/3 bias)
MBE535
2001 Oct 02
27
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
8
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
9
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see
"Handling MOS Devices" ).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DD
supply voltage
-
0.5
+11.0
V
V
LCD
LCD supply voltage
V
DD
-
11.0
V
DD
V
V
I
input voltage SDA, SCL, CLK, SYNC, SA0, OSC, A0 to A2
V
SS
-
0.5
V
DD
+ 0.5
V
V
O
output voltage S0 to S39, BP0 to BP3
V
LCD
-
0.5
V
DD
+ 0.5
V
I
I
DC input current
-
20
mA
I
O
DC output current
-
25
mA
I
DD
, I
SS
, I
LCD
V
DD
, V
SS
or V
LCD
current
-
50
mA
P
tot
total power dissipation
-
400
mW
P
O
power dissipation per output
-
100
mW
T
stg
storage temperature
-
65
+150
C
2001 Oct 02
28
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
10 DC CHARACTERISTICS
V
DD
= 2 to 9 V; V
SS
= 0 V; V
LCD
= V
DD
-
2 V to V
DD
-
9 V; T
amb
=
-
40 to +85
C; unless otherwise specified.
Notes
1. V
LCD
V
DD
-
3 V for
1
/
3
bias.
2. LCD outputs are open-circuit; inputs at V
SS
or V
DD
; external clock with 50% duty factor; I
2
C-bus inactive.
3. Resets all logic when V
DD
< V
POR
.
4. Periodically sampled, not 100% tested.
5. Outputs measured one at a time.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DD
supply voltage
2
-
9
V
V
LCD
LCD supply voltage
note 1
V
DD
-
9
-
V
DD
-
2
V
I
DD
supply current
note 2
normal mode
f
clk
= 200 kHz
-
-
180
A
power-saving mode
f
clk
= 35 kHz; V
DD
= 3.5 V;
V
LCD
= 0 V; A0, A1 and A2
connected to V
SS
-
-
60
A
Logic
V
IL
LOW-level input voltage
V
SS
-
0.3V
DD
V
V
IH
HIGH-level input voltage
0.7V
DD
-
V
DD
V
V
OL
LOW-level output voltage
I
OL
= 0 mA
-
-
0.05
V
V
OH
HIGH-level output voltage
I
OH
= 0 mA
V
DD
-
0.05
-
-
V
I
OL1
LOW-level output current
CLK, SYNC
V
OL
= 1 V; V
DD
= 5 V
1
-
-
mA
I
OH1
HIGH-level output current CLK
V
OH
= 4 V; V
DD
= 5 V
1
-
-
mA
I
OL2
LOW-level output current
SDA and SCL
V
OL
= 0.4 V; V
DD
= 5 V
3
-
-
mA
I
L1
leakage current SA0, A0 to A2,
CLK, SDA and SCL
V
I
= V
DD
or V
SS
-
-
1
A
I
L2
leakage current OSC
V
I
= V
DD
-
-
1
A
I
pd
A0, A1, A2 and OSC pull-down
current
V
I
= 1 V; V
DD
= 5 V
20
50
150
A
R
SYNC
pull-up resistor (SYNC)
20
50
150
k
V
POR
Power-on reset voltage level
note 3
-
1.0
1.6
V
C
I
input capacitance
note 4
-
-
7
pF
LCD outputs
V
BP
DC voltage component BP0 to BP3
C
BP
= 35 nF
-
20
-
mV
V
S
DC voltage component S0 to S39
C
S
= 5 nF
-
20
-
mV
R
BP
output resistance BP0 to BP3
note 5; V
LCD
= V
DD
-
5 V
-
-
5
k
R
S
output resistance S0 to S39
note 5; V
LCD
= V
DD
-
5 V
-
-
7.5
k
2001 Oct 02
29
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
11 AC CHARACTERISTICS
V
DD
= 2 to 9 V; V
SS
= 0 V; V
LCD
= V
DD
-
2 V to V
DD
-
9 V; T
amb
=
-
40 to +85
C; unless otherwise specified.
Notes
1. At f
clk
< 125 kHz, I
2
C-bus maximum transmission speed is derated.
2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
clk
oscillator frequency on pin CLK
normal mode
V
DD
= 5 V; note 1
125
200
288
kHz
power-saving mode
V
DD
= 3.5 V
21
31
48
kHz
t
clkH
CLK HIGH time
see Fig.21
1
-
-
s
t
clkL
CLK LOW time
1
-
-
s
t
PSYNC
SYNC propagation delay time
-
-
400
ns
t
SYNCL
SYNC LOW time
1
-
-
s
t
PLCD
driver delays with test loads
V
LCD
= V
DD
-
5 V; see Fig.20
-
-
30
s
Timing characteristics: I
2
C-bus; note 2; see Fig.22
t
SW
tolerable spike width on bus
-
-
100
ns
t
BUF
bus free time
4.7
-
-
s
t
HD;STA
START condition hold time
4.0
-
-
s
t
SU;STA
set-up time for a repeated START condition
4.7
-
-
s
t
LOW
SCL LOW time
4.7
-
-
s
t
HIGH
SCL HIGH time
4.0
-
-
s
t
r
SCL and SDA rise time
-
-
1
s
t
f
SCL and SDA fall time
-
-
0.3
s
C
B
capacitive bus line load
-
-
400
pF
t
SU;DAT
data set-up time
250
-
-
ns
t
HD;DAT
data hold time
0
-
-
ns
t
SU;STO
set-up time for STOP condition
4.0
-
-
s
Fig.20 Test loads.
MBE544
3.3 k
1.5 k
0.5VDD
VDD
VDD
SDA,
SCL
CLK
1 nF
BP0 to BP3, and
S0 to S39
(2%)
(2%)
6.8
VDD
SYNC
(2%)
2001 Oct 02
30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Fig.21 Driver timing waveforms.
handbook, full pagewidth
MBE545
0.7VDD
0.3VDD
1/ fclk
t
PSYNC
t clkH
t clkL
0.7VDD
0.3VDD
SYNC
CLK
0.5 V
0.5 V
t PLCD
BP0 to BP3,
and S0 to S39
t
PSYNC
t
SYNCL
(VDD = 5 V)
Fig.22 I
2
C-bus timing waveforms.
handbook, full pagewidth
SDA
MGA728
SDA
SCL
t SU;STA
t
SU;STO
t
HD;STA
t BUF
t LOW
t HD;DAT
t HIGH
t r
t f
t SU;DAT
2001 Oct 02
31
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
11.1
Typical supply current characteristics
Fig.23
-
I
SS
as a function of f
frame
.
V
DD
= 5 V; V
LCD
= 0 V; T
amb
= 25
C.
0
200
50
0
10
MBE530
20
30
40
100
I
SS
(
A
)
f
(Hz)
frame
normal
mode
power-saving
mode
Fig.24
-
I
LCD
as a function of f
frame
.
V
DD
= 5 V; V
LCD
= 0 V; T
amb
= 25
C.
0
200
50
0
10
MBE529
20
30
40
100
I
LCD
(
A
)
f
(Hz)
frame
Fig.25 I
SS
as a function of V
DD
.
V
LCD
= 0 V; external clock; T
amb
= 25
C.
handbook, halfpage
0
10
50
0
10
MBE528 - 1
20
30
40
5
I
SS
(
A
)
V
(V)
DD
power-saving mode
f = 35 kHz
clk
normal mode
f = 200 kHz
clk
Fig.26 I
LCD
as a function of V
DD
.
V
LCD
= 0 V; external clock; f
clk
= nominal frequency.
handbook, halfpage
0
10
50
0
10
MBE527 - 1
20
30
40
5
V
(V)
DD
I
LCD
(
A
)
85 C
o
25 C
o
40 C
o
2001 Oct 02
32
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
11.2
Typical characteristics of LCD outputs
Fig.27 R
O(max)
as a function of V
DD
.
V
LCD
= 0 V; T
amb
= 25
C.
handbook, halfpage
6
0
10
-1
MBE532 - 1
1
10
3
V
(V)
DD
R S
R BP
R
O(max)
(k
)
Fig.28 R
O(max)
as a function of T
amb
.
V
DD
= 5 V; V
LCD
= 0 V.
40
0
40
120
2.5
0
2.0
MBE526
80
1.5
1.0
0.5
R S
R BP
R
O(max)
(k
)
Tamb( C)
o
2001
Oct
02
33
Philips Semiconductors
Product specification
Univ
ersal
LCD
dr
iv
er
f
o
r
l
o
w
m
ultiple
x
r
ates
PCF8576
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12
APPLICA
TION INFORMA
TION
a
ndbook, full pagewidth
PCF8576T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SDA
SCL
SYNC
CLK
V
OSC
A0
A1
A2
SA0
V
V
BP0
BP2
BP1
BP3
S0
S1
S2
S3
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
34
33
S17
S7
S8
S9
S10
S11
32
31
30
29
S16
S15
S13
S14
S12
DD
SS
LCD
PCF8576T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
BP0
BP2
BP1
BP3
S40
S41
S42
S43
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
34
33
S57
S47
S48
S49
S50
S51
S51
S52
S53
32
31
30
29
S56
S55
S53
S54
S52
S50
S39
S40
S13
S12
open
S10
S11
S0
S79
backplanes
segments
MBK281
SDA
SCL
SYNC
CLK
V
V
V
DD
SS
LCD
Fig.29 Single plane wiring of packaged PCF8576Ts.
2001 Oct 02
34
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
12.1
Chip-on-glass cascadability in single plane
In chip-on-glass technology, where driver devices are
bonded directly onto glass of the LCD, it is important that
the devices may be cascaded without the crossing of
conductors, but the paths of conductors can be continued
on the glass under the chip. All of this is facilitated by the
PCF8576 bonding pad layout (see Fig.30). Pads needing
bus interconnection between all PCF8576s of the cascade
are V
DD
, V
SS
, V
LCD
, CLK, SCL, SDA and SYNC. These
lines may be led to the corresponding pads of the next
PCF8576 through the wide opening between V
LCD
pad
and the backplane output pads. The only bus line that does
not require a second opening to lead through to the next
PCF8576 is V
LCD
, being the cascade centre. The placing
of V
LCD
adjacent to V
SS
allows the two supplies to be
connected together.
When an external clocking source is to be used, OSC of all
devices should be connected to V
DD
. The pads OSC,
A0, A1, A2 and SA0 have been placed between
V
SS
and V
DD
to facilitate wiring of oscillator, hardware
subaddress and slave address.
13 BONDING PAD INFORMATION
Fig.30 Bonding pad locations.
Bonding pad dimensions: 120
120
m.
Gold bump dimensions: 94
94
25
m.
handbook, full pagewidth
MBK282
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
BP3
BP1
BP2
BP0
VLCD
VSS
SA0
A2
A1
A0
OSC
V
DD
CLK
SCL
SDA
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
SYNC
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
14
PCF8576
x
y
0
0
cascade
centre
3.07 mm
4.12
mm
2001 Oct 02
35
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
Table 15 Bonding pad locations (dimensions in
m)
All x and y coordinates are referenced to centre of chip
(see Fig.30).
Table 16 Bonding pad dimensions
SYMBOL
PAD
COORDINATES
x
y
SDA
1
-
155
-
1900
SCL
2
45
-
1900
SYNC
3
245
-
1900
CLK
4
445
-
1900
V
DD
5
645
-
1900
OSC
6
865
-
1900
A0
7
1105
-
1900
A1
8
1375
-
1900
A2
9
1375
-
1700
SA0
10
1375
-
1500
V
SS
11
1375
-
1300
V
LCD
12
1375
-
1100
BP0
13
1375
300
BP2
14
1375
500
BP1
15
1375
700
BP3
16
1375
900
S0
17
1375
1100
S1
18
1375
1300
S2
19
1375
1500
S3
20
1375
1700
S4
21
1375
1900
S5
22
1105
1900
S6
23
865
1900
S7
24
645
1900
S8
25
445
1900
S9
26
245
1900
S10
27
45
1900
S11
28
-
155
1900
S12
29
-
355
1900
S13
30
-
555
1900
S14
31
-
755
1900
S15
32
-
955
1900
S16
33
-
1155
1900
S17
34
-
1375
1900
S18
35
-
1375
1660
S19
36
-
1375
1420
S20
37
-
1375
1200
S21
38
-
1375
1000
S22
39
-
1375
800
S23
40
-
1375
600
S24
41
-
1375
400
S25
42
-
1375
200
S26
43
-
1375
-
200
S27
44
-
1375
-
400
S28
45
-
1375
-
600
S29
46
-
1375
-
800
S30
47
-
1375
-
1000
S31
48
-
1375
-
1200
S32
49
-
1375
-
1420
S33
50
-
1375
-
1660
S34
51
-
1375
-
1900
S35
52
-
1155
-
1900
S36
53
-
955
-
1900
S37
54
-
755
-
1900
S38
55
-
555
-
1900
S39
56
-
355
-
900
Pad pitch
200
m
Pad size, aluminium
120
120
m
Gold bump dimensions
94
94
25
m
SYMBOL
PAD
COORDINATES
x
y
2001 Oct 02
36
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
14 TRAY INFORMATION: PCF8576U
handbook, full pagewidth
x
y
F
H
MGU431
D
E
A
G
1,1
x,1
2,1
1,2
1,y
x,y
C
B
M
J
A
A
SECTION A-A
Fig.31 Tray details.
For dimensions see Table 18.
Table 17 Tray dimensions (see Fig.33)
handbook, halfpage
MGU432
PC8576U
Fig.32 Tray alignment.
The orientation of the IC in a pocket is indicated by the
position of the IC type name on the die surface with respect to
the chamfer on the upper left corner of the tray.
SYMBOL
DESCRIPTION
VALUE
A
pocket pitch; x direction
6.32 mm
B
pocket pitch; y direction
6.32 mm
C
pocket width; x direction
4.55 mm
D
pocket width; y direction
4.55 mm
E
tray width; x direction
50.67 mm
F
tray width; y direction
50.67 mm
G
cut corner to pocket 1,1 centre
6.32 mm
H
cut corner to pocket 1,1 centre
6.32 mm
J
tray thickness
3.94 mm
M
pocket depth
0.61 mm
x
number of pockets; x direction
7
y
number of pockets; y direction
7
2001 Oct 02
37
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
15 TRAY INFORMATION: PCF8576U/2
handbook, full pagewidth
1,1
x,1
2,1
1,2
1,y
x,y
x
y
F
H
G
D
A
C
B
MGW014
E
K
L
M
J
A
A
SECTION A-A
Fig.33 Tray details.
For dimensions see Table 17.
Table 18 Tray dimensions (see Fig.31)
handbook, halfpage
MGW015
PCF8576U/2
Fig.34 Tray alignment.
The orientation of the IC in a pocket is indicated by the
position of the IC type name on the die surface with respect to
the chamfer on the upper left corner of the tray.
SYMBOL
DESCRIPTION
VALUE
A
pocket pitch; x direction
5.33 mm
B
pocket pitch; y direction
7.11 mm
C
pocket width; x direction
3.43 mm
D
pocket width; y direction
4.67 mm
E
tray width; x direction
50.67 mm
F
tray width; y direction
50.67 mm
G
cut corner to pocket 1,1 centre
6.67 mm
H
cut corner to pocket 1,1 centre
7.56 mm
J
tray thickness
3.94 mm
K
tray cross section
1.76 mm
L
tray cross section
2.46 mm
M
pocket depth
0.89 mm
x
number of pockets; x direction
8
y
number of pockets; y direction
6
2001 Oct 02
38
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
16 PACKAGE OUTLINES
UNIT
A
1
A
2
A
3
b
p
c
D
(1)
E
(2)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
0.3
0.1
3.0
2.8
0.25
0.42
0.30
0.22
0.14
21.65
21.35
11.1
11.0
0.75
15.8
15.2
1.45
1.30
0.90
0.55
7
0
o
o
0.1
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
1.6
1.4
SOT190-1
96-04-02
97-08-11
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
X
(A )
3
A
y
56
29
28
1
pin 1 index
0.012
0.004
0.12
0.11
0.017
0.012
0.0087
0.0055
0.85
0.84
0.44
0.43
0.0295
2.25
0.089
0.62
0.60
0.057
0.051
0.035
0.022
0.004
0.2
0.008
0.004
0.063
0.055
0.01
0
5
10 mm
scale
VSO56: plastic very small outline package; 56 leads
SOT190-1
A
max.
3.3
0.13
Note
1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
2001 Oct 02
39
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
17 SOLDERING
17.1
Introduction to soldering surface mount
packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"Data Handbook IC26; Integrated Circuit Packages"
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
17.2
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250
C. The top-surface temperature of the
packages should preferable be kept below 220
C for
thick/large packages, and below 235
C for small/thin
packages.
17.3
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
For packages with leads on two sides and a pitch (e):
larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
For packages with leads on four sides, the footprint must
be placed at a 45
angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
17.4
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300
C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320
C.
2001 Oct 02
40
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
17.5
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45
angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE
SOLDERING METHOD
WAVE
REFLOW
(1)
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not suitable
(2)
suitable
PLCC
(3)
, SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended
(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended
(5)
suitable
2001 Oct 02
41
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
18 DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DATA SHEET STATUS
(1)
PRODUCT
STATUS
(2)
DEFINITIONS
Objective specification
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary specification
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product specification
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
19 DEFINITIONS
Short-form specification
The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition
Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
20 DISCLAIMERS
Life support applications
These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Bare die
All die are tested and are guaranteed to
comply with all data sheet limits up to the point of wafer
sawing for a period of ninety (90) days from the date of
Philips' delivery. If there are data sheet limits not
guaranteed, these will be separately indicated in the data
sheet. There are no post packing tests performed on
individual die or wafer. Philips Semiconductors has no
control of third party procedures in the sawing, handling,
packing or assembly of the die. Accordingly, Philips
Semiconductors assumes no liability for device
functionality or performance of the die or systems after
third party sawing, handling, packing or assembly of the
die. It is the responsibility of the customer to test and
qualify their application in which the die is used.
2001 Oct 02
42
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
21 PURCHASE OF PHILIPS I
2
C COMPONENTS
Purchase of Philips I
2
C components conveys a license under the Philips' I
2
C patent to use the
components in the I
2
C system provided the system conforms to the I
2
C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2001 Oct 02
43
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8576
NOTES
Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands
403512/04/pp
44
Date of release:
2001 Oct 02
Document order number:
9397 750 08044
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