Document Outline
- FEATURES
- DESCRIPTION
- PIN CONFIGURATION
- ORDERING INFORMATION
- PIN DESCRIPTION
- BLOCK DIAGRAM
- FUNCTION TABLE
- POWER-DOWN MODE
- SPREAD SPECTRUM FUNCTION
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- POWER MANAGEMENT
- DC ELECTRICAL CHARACTERISTICS
- AC ELECTRICAL CHARACTERISTICS
- Host clock outputs
- IOCLK outputs
- USB clock output, 48MHz
- REF clock output
- All outputs
- Group offset limits
- AC WAVEFORMS
- PACKAGING
- Data sheet status
- Definitions
- Disclaimers
Philips
Semiconductors
PCK2022R
CK00 (100/133 MHz) spread spectrum
differential system clock generator
Product specification
Supersedes data of 2000 Aug 08
2000 Nov 13
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum
differential system clock generator
2
2000 Nov 13
8532225 25005
FEATURES
3.3 V operation
Eight differential CPU clock pairs
One IO clock at 33 MHz and 66 MHz
Two 48 MHz clocks at 3.3 V
One 14.318 MHz reference clock
Power management control pins
Host clock jitter less than 200 ps cycle-to-cycle
Host clock skew less than 150 ps pin-to-pin
Spread Spectrum capability
DESCRIPTION
The PCK2022R is a clock synthesizer/driver for a Pentium III
TM
and
other similar processors
The PCK2022R has eight differential pair CPU current source
outputs, one 33/66 MHz output which is configurable on power-up,
two 48 MHz clocks which can be disabled on power-up, and one
3.3 V reference clock at 14.318 MHz which can also be disabled on
power-up. All clock outputs meet Intel's drive strength, rise/fall times,
jitter, accuracy, and skew requirements.
The part possesses a dedicated power-down input pin for power
management control. This input is synchronized on chip, and
ensures glitch-free output transitions. In addition, the part can be
configured to disable the 48 MHz outputs for lower power operation
and an increase in the performance of the functioning outputs. The
IOCLK and REFCLK can also be disabled for the highest
performance of the Host outputs.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
IOCLK
48M_0/SELA
48M_1/SELB
V
SS
V
DD
HCLK0
HCLKB0
V
SS
HCLK1
HCLKB1
SEL100/133
V
SS
V
DDA
V
SSA
PWRDWN
V
DD
HCLK4
V
SS
HCLKB4
HCLK5
HCLKB5
V
DD
V
DD
13
14
15
16
17
18
31
32
33
34
35
36
HCLK2
HCLKB2
V
SS
HCLK3
HCLKB3
HCLK6
V
SS
HCLKB6
HCLK7
HCLKB7
V
DD
19
30
V
DD
REFCLK/SELC
20
21
22
23
24
25
26
27
28
29
SPREAD
V
SS
XIN
XOUT
V
DD
MULTSEL0
V
SSA
MULTSEL1
I
REF
V
DDA
V
DD
V
SS
SW00665
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
48-Pin Plastic TSSOP
0
C to +70
C
PCK2022R DGG
SOT362-1
Intel and Pentium III are trademarks of Intel Corporation.
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
3
PIN DESCRIPTION
PIN(S)
SYMBOL
FUNCTION
1
IOCLK
Dual frequency pin which can operate at either 33 MHz or 66 MHz per the selection table.
3, 4
48M_0/SELA
48M_1/SELB
3.3 V fixed 48 MHz clock outputs. During power-up pins function as latched inputs that enable SELA and
SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in.
7, 8
HCLK0
HCLKB0
Host output pair 0
10, 11
HCLK1
HCLKB1
Host output pair 1
13, 14
HCLK2
HCLKB2
Host output pair 2
16, 17
HCLK3
HCLKB3
Host output pair 3
42, 21
HCLK4
HCLKB4
Host output pair 4
39, 38
HCLK5
HCLKB5
Host output pair 5
36, 35
HCLK6
HCLKB6
Host output pair 6
33, 32
HCLK7
HCLKB7
Host output pair 7
19
REFCLK/SELC
3.3 V fixed 14.318 MHz output. During power-up, pin functions as a latched input that enables SELC prior
to the pin being used for the clock output. Part must be clocked to latch data in.
20
SPREAD
Enables spread spectrum mode when held LOW on differential host outputs and 33 MHz IOCLK clocks.
Asserts LOW.
21
XIN
Crystal input
22
XOUT
Crystal output
26
I
REF
This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the correct current.
29, 30
MULTSEL0
MULTSEL1
Select input pin used to control the scaling of the HCLK and HCLKB output current.
44
PWRDWN
Device enters power-down mode when held LOW. Asserts LOW.
48
SEL100/133
Select input pin for enabling 133 MHz or 100 MHz CPU outputs
2, 6, 12,
18, 24, 31,
37, 43
V
DD3
3.3 V power supply
5, 9, 15,
21, 28, 34,
40, 47
GND
Ground
25, 46
AV
DD
3.3 V power supply for analog circuits
27, 45
AGND
Ground for analog circuits
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
4
BLOCK DIAGRAM
14.318 MHz
OSC
XIN
XOUT
USB PLL
PWRDWN
PWRDWN
PWRDWN
PWRDWN
PWRDWN
SYS PLL
LOGIC
SPREAD
MULTSEL0
REF[0] (14.318 MHz)
48MHz[0..1] (3 V)
HOST[0..7] (100/133 MHz)
HOST_BAR[0..7] (100/133 MHz)
IOCLK (33/66 MHz)
SW00666
MULTSEL1
PWRDWN
SEL100/133
IBIAS
I
REF
SELA/B
SELC
FUNCTION TABLE
SEL100/133
SELA
SELB
SELC
HOST
48MHz
IOCLK
REFCLK
0
0
0
0
100 MHz
48 MHz
33.3 MHz
14.318 MHz
0
0
0
1
100 MHz
48 MHz
66.7 MHz
14.318 MHz
0
0
1
0
100 MHz
Hi-Z
33.3 MHz
14.318 MHz
0
0
1
1
100 MHz
Hi-Z
66.7 MHz
14.318 MHz
0
1
0
0
100 MHz
Hi-Z
Low
Low
0
1
0
1
100 MHz
48 MHz
1
33.3 MHz
14.318 MHz
0
1
1
0
Low
Hi-Z
Hi-Z
Hi-Z
0
1
1
1
100 MHz
48 MHz
1
66.7 MHz
14.318 MHz
1
0
0
0
133 MHz
48 MHz
33.3 MHz
14.318 MHz
1
0
0
1
133 MHz
48 MHz
66.7 MHz
14.318 MHz
1
0
1
0
133 MHz
Hi-Z
33.3 MHz
14.318 MHz
1
0
1
1
133 MHz
Hi-Z
66.7 MHz
14.318 MHz
1
1
0
0
200 MHz
48 MHz
33.3 MHz
14.318 MHz
1
1
0
1
133 MHz
48 MHz
1
33.3 MHz
14.318 MHz
1
1
1
0
TCLK/2
TCLK/4
TCLK/4
TCLK
1
1
1
1
133 MHz
48 MHz
1
66.7 MHz
14.318 MHz
NOTE:
1. These frequencies are for debug, and thus can vary a small amount from the values listed at the vendor's discretion.
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
5
Table 1. Host swing select functions
MULTSEL0
MULTSEL1
BOARD
IMPEDANCE
I
REF
I
OH
V
OH
@ IREF = 2.32 mA
0
0
60
R
REF
= 475 1%
I
REF
= 2.32 mA
I
OH
= 5*I
REF
0.71 V
0
0
50
R
REF
= 475 1%
I
REF
= 2.32 mA
I
OH
= 5*I
REF
0.59 V
0
1
60
R
REF
= 475 1%
I
REF
= 2.32 mA
I
OH
= 6*I
REF
0.85 V
0
1
50
R
REF
= 475 1%
I
REF
= 2.32 mA
I
OH
= 6*I
REF
0.71 V
1
0
60
R
REF
= 475 1%
I
REF
= 2.32 mA
I
OH
= 4*I
REF
0.56 V
1
0
50
R
REF
= 475 1%
I
REF
= 2.32 mA
I
OH
= 4*I
REF
0.47 V
1
1
60
R
REF
= 475 1%
I
REF
= 2.32 mA
I
OH
= 7*I
REF
0.99 V
1
1
50
R
REF
= 475 1%
I
REF
= 2.32 mA
I
OH
= 7*I
REF
0.82 V
0
0
30
R
REF
= 221 1%
I
REF
= 5 mA
I
OH
= 5*I
REF
0.75 V
0
0
25
R
REF
= 221 1%
I
REF
= 5 mA
I
OH
= 5*I
REF
0.62 V
0
1
30
R
REF
= 221 1%
I
REF
= 5 mA
I
OH
= 6*I
REF
0.90 V
0
1
25
R
REF
= 221 1%
I
REF
= 5 mA
I
OH
= 6*I
REF
0.75 V
1
0
30
R
REF
= 221 1%
I
REF
= 5 mA
I
OH
= 4*I
REF
0.60 V
1
0
25
R
REF
= 221 1%
I
REF
= 5 mA
I
OH
= 4*I
REF
0.50 V
1
1
30
R
REF
= 221 1%
I
REF
= 5 mA
I
OH
= 7*I
REF
1.05 V
1
1
25
R
REF
= 221 1%
I
REF
= 5 mA
I
OH
= 7*I
REF
0.84 V
NOTE:
The outputs are optimized for the configurations shown shaded.
CONDITIONS
CONFIGURATION
LOAD
MIN.
MAX.
I
OUT
V
DD
= 3.3 V
All combinations;
see Table 1 above
Nominal test load for
given configuration
7% of I
OH
see Table 1 above
+7% of I
OH
see Table 1 above
I
OUT
V
DD
= 3.3 V
5%
All combinations;
see Table 1 above
Nominal test load for
given configuration
12% of I
OH
see Table 1 above
+12% of I
OH
see Table 1 above
POWER-DOWN MODE
PWRDWN
HCLK/HCLKB
IOCLK
48MHz
REFCLK
Asserts LOW
0 = Active
Host = 2*I
REF
Host_bar = undriven
LOW
LOW
LOW
NOTE:
The differential outputs should have a voltage forced across them when power-down is asserted.
SPREAD SPECTRUM FUNCTION
SPREAD #
FUNCTION
48 MHz PLL
REFCLK
1
Host/IOCLK
No Spread
No Spread
0
Host/IOCLK
Down spread 0.5%
No Spread
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
6
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
DD3
DC 3.3 V supply
0.5
4.6
V
I
IK
DC input diode current
V
I
< 0
50
mA
V
I
DC input voltage
Note 2
0.5
V
DD
V
I
OK
DC output diode current
V
O
> V
DD
or V
O
< 0
50
mA
V
O
DC output voltage
Note 2
0.5
V
DD
+0.5
V
I
O
DC output source or sink current
V
O
= 0 to V
DD
50
mA
T
stg
Storage temperature range
65
+150
C
P
tot
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range 40
C to +125
C;
above +55
C derate linearly with 11.3 mW/K
850
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other condition beyond those indicated under "recommended operating condition" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage rating may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
DD3
DC 3.3 V supply voltage
3.135
3.465
V
AV
DD
DC 3.3 V analog supply voltage
3.135
3.465
V
C
L
Capacitive load on:
IOCLK
Must meet IOCLK 2.1 requirements
10
30
pF
48 MHz clock
1 device load
10
20
pF
REF
1 device load
10
20
pF
f
ref
Reference frequency, oscillator normal value
14.31818
14.31818
MHz
T
amb
Operating ambient temperature range in free air
0
+70
C
POWER MANAGEMENT
CONDITION
MAXIMUM 3.3 V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAPACITANCE LOADS
V
DDL
= 3.465 V
ALL STATIC INPUTS = V
DD3
OR V
SS
Power-down mode (PWRDWN = 0)
60 mA
Full active 100/133 MHz
250 mA
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
7
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
C to +70
C
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
V
DD
(V)
OTHER
MIN
TYP
MAX
UNIT
V
IH
HIGH level input voltage
3.135 to 3.465
2.0
V
DD
+0.3
V
V
IL
LOW level input voltage
3.135 to 3.465
V
SS
0.3
0.8
V
V
OH3
3.3 V output HIGH voltage
REF, 48M
3.135 to 3.465
I
OH
= 1 mA
2.0
V
V
OL3
3.3 V output LOW voltage
REF, 48M
3.135 to 3.465
I
OH
= 1 mA
0.4
V
V
OHP
3.3 V output HIGH voltage
IOCLK
3.135 to 3.465
I
OH
= 1 mA
2.4
V
V
OLP
3.3 V output LOW voltage
IOCLK
3.135 to 3.465
I
OH
= 1 mA
0.55
V
I
O
Output HIGH current
3.135
V
OUT
= 1.0 V
Type 5
33
mA
I
OH
IOCLK
3.465
V
OUT
= 3.135 V
y
12 55
33
mA
I
O
Output HIGH current
3.135
V
OUT
= 1.0 V
Type 3
29
mA
I
OH
48 MHz, REF
3.465
V
OUT
= 3.135 V
y
20 60
23
mA
I
O
Output HIGH current
3 135 to 3 465
0.66 V
Type X1
11
mA
I
OH
HOST/HOST_BAR
3.135 to 3.465
0.76 V
Type X1
12.7
mA
I
O
Output LOW current
3.135
V
OUT
= 1.95 V
Type 5
30
mA
I
OL
IOCLK
3.465
V
OUT
= 0.4 V
y
12 55
38
mA
I
O
Output LOW current
3.135
V
OUT
= 1.95 V
Type 3
29
mA
I
OL
48 MHz, REF
3.465
V
OUT
= 0.4 V
y
20 60
27
mA
V
O
HOST/HOST BAR
V
SS
= 0 V
R
S
= 33.2
Type X1
0 05
V
V
OL
HOST/HOST_BAR
V
SS
= 0 V
S
R
P
= 49.9
Type X1
0.05
V
I
I
Input leakage current
3.465
0 < V
IN
< V
DD3
50
50
A
I
OZ
3-State output
OFF-State current
3.465
V
OUT
=
V
DD
or GND
I
O
= 0
10
A
C
in
Input pin capacitance
5
pF
C
out
Output pin capacitance
6
pF
C
xtal
Crystal input capacitance
13.5
22.5
pF
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
8
AC ELECTRICAL CHARACTERISTICS
V
DD3
= 3.3 V
5%; f
crystal
= 14.31818 MHz
Host clock outputs
T
amb
= 0
C to +70
C; see Figure 1 for waveforms and Figure 6 for test setup.
LIMITS
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNITS
NOTES
MIN
MAX
MIN
MAX
t
PKP
HOST CLK average period
7.5
7.65
10.0
10.2
ns
11, 14, 20
Abs Min Period
Absolute minimum host clock period
7.35
N/A
9.85
N/A
ns
11, 14, 20
t
RISE
HOST CLK rise time
175
700
175
700
ns
11, 15, 20
t
FALL
HOST CLK fall time
175
700
175
700
ps
11, 15, 20
t
JITTER
HOST_CLK cycle-to-cycle jitter
150
150
ps
11, 12, 14, 20
DUTY CYCLE
Output duty cycle
45
55
45
55
%
11, 14, 20
t
SKEW
HOST CLK pin-to-pin skew
150
150
ps
11, 14, 20
Rise/Fall Match-
ing
Rise and Fall time matching
20%
20%
11, 16, 20
V
crossover
40% V
OH
55% V
OH
40% V
OH
55% V
OH
V
11, 14, 20
REFER TO NOTES ON PAGE 9.
IOCLK outputs
T
amb
= 0
C to +70
C
LIMITS
SYMBOL
PARAMETER
33 MHz MODE
66 MHz MODE
UNITS
NOTES
MIN
MAX
MIN
MAX
t
PKP
IOCLK period
30.0
N/A
15.0
N/A
ns
2, 3, 9, 20
t
PKH
IOCLK HIGH time
12.0
N/A
6.0
N/A
ns
5, 10, 20
t
PKL
IOCLK LOW time
12.0
N/A
6.0
N/A
ns
6, 10, 20
t
RISE
IOCLK rise time
0.5
2.0
0.5
2.0
ns
8, 20
t
FALL
IOCLK fall time
0.5
2.0
0.5
2.0
ns
8, 20
t
JITTER
Cycle-to-cycle jitter
200
200
ps
18, 20
DUTY CYCLE
Output duty cycle
45
55
45
55
%
18, 20
REFER TO NOTES ON PAGE 9.
USB clock output, 48MHz
T
amb
= 0
C to +70
C; lump capacitance test load = 20 pF
LIMITS
SYMBOL
PARAMETER
48 MHz MODE
UNITS
NOTES
MIN
MAX
f
Frequency, actual
48.08
MHz
4
f
D
Deviation from 48 MHz
+167
ppm
4
t
HKL
3V48MHZCLK LOW time
5.05
N/A
ns
20
t
RISE
3V48MHZCLK rise time
1.0
4.0
ns
8, 20
t
FALL
3V48MHZCLK fall time
1.0
4.0
ns
8, 20
t
JITTER
Cycle-to-cycle jitter
250
ps
18, 20
DUTY CYCLE
Output duty cycle
45
55
%
18, 20
REFER TO NOTES ON PAGE 9.
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
9
REF clock output
T
amb
= 0
C to +70
C; lump capacitance test load = 20 pF
LIMITS
SYMBOL
PARAMETER
48 MHz MODE
UNITS
NOTES
MIN
MAX
f
Frequency, actual
14.318
MHz
17, 20
t
HKL
REFCLK LOW time
30
37
ns
20
t
HKH
REFCLK HIGH time
30
37
ns
20
t
JITTER
Cycle-to-cycle jitter
300
ps
18, 20
DUTY CYCLE
Output duty cycle
45
55
%
18, 20
REFER TO NOTES ON PAGE 9.
All outputs
T
amb
= 0
C to +70
C
LIMITS
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNITS
NOTES
MIN
MAX
MIN
MAX
t
PZL
, t
PZH
Output enable delay (all outputs)
1.0
10.0
1.0
10.0
ns
20
t
PZL
, t
PZH
Output disable delay (all outputs)
1.0
10.0
1.0
10.0
ns
20
t
STABLE
All clock stabilization from power-up
3
3
ms
7, 20
REFER TO NOTES ON PAGE 9.
Group offset limits
GROUP
OFFSET
MEASUREMENT LOADS
(LUMPED)
MEASUREMENT POINTS
NOTES
Host to IOCLK
1.5 3.5 ns
Host leads
IOCLK @ 30 pF
Host @ Cross point
IOCLK @ 1.5 V
19, 20
NOTES TO THE AC TABLES:
1. Output drivers must have monotonic rise/fall times through the specified V
OL
/V
OH
levels.
2. Period, jitter, offset, and skew measured on rising edge at 1.5 V for 3.3 V clocks.
3. The IOCLK clock is the Host clock divided by 4 in 33 MHz mode and divided by 2 in 66 MHz mode at Host = 133 MHz.
IOCLK clock is the Host clock divided by 3 in 33 MHz and divided by 2/3 in 66 MHz mode at Host = 100 MHz.
4. Frequency accuracy of 48 MHz must be +167 ppm to match USB default.
5. t
HKH
is measured at 2.4 V for 3.3 V outputs, as shown in Figure 7.
6. t
HKL
is measured at 0.4 V for all outputs as shown in Figure 7.
7. the time is specified from when V
DDQ
achieves its normal operating level (typical condition V
DDQ
= 3.3 V) until the frequency output is stable
and operating within specification.
8. t
RISE
and t
FALL
are measured as a transition through the threshold region V
OL
= 0.4 V and V
OH
= 2.4 V (1 mA) JEDEC specification.
9. The average period over any 1
s period of time must be greater than the minimum specified period.
10. Calculated at minimum edge rate (1 V/ns) to guarantee 4555% duty cycle. Pulse width is required to be wider at faster edge rate to ensure
duty specification is met.
11. Test load is R
S
= 33.2
, R
P
= 49.9
.
12. Must be guaranteed in a realistic system environment.
13. Configured for V
OH
= 0.71 V in a 50
environment.
14. Measured at crossing points.
15. Measured at 20% to 80%.
16. Determined as a fraction of 2*(t
RP
t
RN
) / (t
RP
+ t
RN
), where t
RP
is a rising edge, and t
RN
is an intersecting falling edge.
17. Frequency generated by crystal oscillator
18. Voltage measure point (V
M
= 1.5 V). V
DD
= 3.3 V.
19. All offsets are to be measured at rising edges.
20. Parameters are guaranteed by design.
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
10
AC WAVEFORMS
V
M
= 1.25 V @ V
DDL
and 1.5 V @ V
DD3
V
X
= V
OL
+ 0.3 V
V
Y
= V
OH
0.3 V
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
50%
HOST CLK
V
OH
V
SS
V
SS
V
OH
t
SKEW
HOST_BAR
CLK
50%
SW00667
50%
t
PERIOD
Figure 1. HOST CLOCK
V
DDL
V
OH
= 2.4 V
V
IH
= 2.0 V
1.5 V
V
IL
= 0.7 V
V
OL
= 0.4 V
V
SS
SYSTEM
MEASUREMENT
POINTS
COMPONENT
MEASUREMENT
POINTS
SW00668
Figure 2. 3.3 V clock waveforms
t
PLZ
t
PZL
V
I
SEL1,
SEL0
GND
V
DD
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
SS
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00662
Figure 3. State enable and disable times
PULSE
GENERATOR
R
T
V
I
DUT
V
O
C
L
V
DD
TEST
S
1
t
PLH
/t
PHL
Open
t
PLZ
/t
PZL
2 V
DD
t
PHZ
/t
PZH
V
SS
Open
V
SS
S
1
2
V
DD
V
DD
= V
DDL
or V
DD3
, depending on the output.
500
500
SW00660
Figure 4. Load circuitry for switching times
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2000 Nov 13
11
SW00669
PWRDWN
HOST CLK
(INTERNAL)
PCICLK
(INTERNAL)
PCICLK
(EXTERNAL)
HOST CLK
(EXTERNAL)
PWRDWN
OSC & VCO
USB (48 MHz)
Figure 5. Power management
DUT
HOST
HOST_BAR
C
L
C
L
R
S
R
S
R
S
= 33.2
R
P
= 50
R
P
= 50
V
DD
CRYSTAL
14.318 MHz
SW00671
Figure 6. HOST CLOCK measurements
t
PKP
t
PKH
t
RISE
t
FALL
t
PKL
3.3V CLOCKING
INTERFACE
2.4 V
1.5 V
0.4 V
SW00659
DUTY CYCLE
Figure 7. 3.3 V clock waveforms
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum
differential system clock generator
2000 Nov 13
12
TSSOP48:
plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum
differential system clock generator
2000 Nov 13
13
NOTES
Philips Semiconductors
Product specification
PCK2022R
CK00 (100/133 MHz) spread spectrum
differential system clock generator
2000 Nov 13
14
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Date of release: 11-00
Document order number:
9397 750 07756
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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