Philips Semiconductors

Product data

PCK2057

70 190 MHz I

C differential 1:10 clock driver

2001 Jun 12

8532253 26485

FEATURES

Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications supporting DDR 200/266/300/333

Full DDR solution provided when used with PCK2002P or
PCK2002PL, and PCK2022RA

1-to-10 differential clock distribution

Very low jitter (

100 ps)

Operation from 2.2 V to 2.7 V AV

and 2.3 V to 2.7 V V

SSTL_2 interface clock inputs and outputs

HCSL to SSTL_2 input conversion

Test mode enables buffers while disabling PLL

Tolerant of Spread Spectrum input clock

3.3 V I

C support with 3.3 V V

2.5 V I

C support with 2.5 V V

Form, fit, and function compatible with CDCV850

DESCRIPTION

The PCK2057 is a high-performance, low-skew, low-jitter zero delay
buffer that distributes a differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs and one differential pair of
feedback clock outputs. The clock outputs are controlled by the
clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the
2-line serial interface (SDA, SCL), and the analog power input
(AV

). The two-line serial interface (I

C) can put the individual

output clock pairs in a high-impedance state. When AV

is tied to

GND, the PLL is turned off and bypassed for test purposes.

The device provides a standard mode (100 kbits) I

C interface for

device control. The implementation is as a slave/receiver. The serial
inputs (SDA, SCL) provide integrated pull-up resistors (typically
100 k

Two 8-bit, 2-line serial registers provide individual enable control for
each output pair. All outputs default to enabled at power-up. Each
output pair can be placed in a high-impedance mode, when a
low-level control bit is written to the control register. The registers
must be accessed in sequential order (i.e., random access of the
registers is not supported). The I

C interface circuit can be supplied

with either 2.5 V or 3.3 V (V

C).

Since the PCK2057 is based on PLL circuitry, it requires a
stabilization time to achieve phase-lock of the PLL. This stabilization
time is required following power-up.

PIN CONFIGURATION

GND

DDQ

GND

DDQ

SCL

CLK

AGND

GND

DDQ

GND

DDQ

GND

DDQ

SDA

FBIN

DDQ

FBOUT

GND

DDQ

SW00506

GND

PIN DESCRIPTION

PINS

SYMBOL

DESCRIPTION

1, 7, 8, 18, 24, 25, 31,

41, 42, 48

GND

Ground

2, 3, 5, 6, 9, 10, 19, 20,

22, 23, 26, 27, 29, 30,
32, 33, 39, 40, 43, 44,

46, 47

, Y

FBOUT, FBOUT

Buffered output
copies of input clock,
CLK

4, 11, 21, 28, 34, 38,

DDQ

2.5 V supply

13, 14, 35, 36

CLK, CLK,

FBIN, FBIN

Differential clock
inputs and feedback
differential clock
inputs

Analog power

AGND

Analog ground

SDA

Serial data

SCL

Serial clock

C power

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DRAWING NUMBER

48-Pin Plastic TSSOP

0 to +70

PCK2057DGG

SOT362-1

Philips Semiconductors

Product data

PCK2057

70 190 MHz I

C differential 1:10 clock driver

2001 Jun 12

C ADDRESS

su01394

R/W

C CONSIDERATIONS

C has been chosen as the serial bus interface to control the PCK2057. I

C was chosen to support the JEDEC proposal JC-42.5 168 Pin

Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I

C devices.

1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only
one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I

C clock driver is used in

the system.

The following address was confirmed by Philips on 09/04/96.

R/W

NOTE: The R/W bit is used by the I

C controller as a data direction bit. A `zero' indicates a transmission (WRITE) to the clock device. A `one'

indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the
R/W bit of the address will always be seen as `zero'. Optimal address decoding of this bit is left to the vendor.

2) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.

3) Logic Levels: I

C logic levels are based on a percentage of V

for the controller and other devices on the bus. Assume all devices are

based on a 3.3 Volt supply.

4) Data Byte Format: Byte format is 8 Bits as described in the following appendices.

5) Data Protocol: To simplify the clock I

C interface, the clock driver serial protocol was specified to use only block writes from the controller.

The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I

C protocol.

The clock driver must meet this protocol which is more rigorous than previously stated I

C protocol. Treat the description from the viewpoint of

controller. The controller "writes" to the clock driver.

SW00911

1 bit

7 bits

8 bits

Start bit

Slave Address

R/W

DUMMY

Ack

Data Byte 1

Ack

Data Byte 2

Ack

Stop

Ack

1 bit

8 bits

NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).

6) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I

specification.

a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of
internal pull-ups on these pins of below 100 k

is discouraged. Assume that the board designer will use a single external pull-up resistor for

each line and that these values are in the 56 k

range. Assume one I

C device per DIMM (serial presence detect), one I

C controller, one

clock driver plus one/two more I

C devices on the platform for capacitive loading purposes.

(b) Input Glitch Filters: Only fast mode I

C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard

mode device and is not required to support this feature.

For specific I

C information, consult the Philips I

C Peripherals Data Handbook IC12 (1997).

Philips Semiconductors

Product data

PCK2057

70 190 MHz I

C differential 1:10 clock driver

2001 Jun 12

SERIAL CONFIGURATION MAP

The serial bits will be read by the clock buffer in the following order:

Byte 0 Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 Bits 7, 6, 5, 4, 3, 2, 1, 0

All unused register bits (Reserved and "--") should be designed as "Don't Care". It is expected that the controller will force all of these bits to a
"0" level.

All register bits labeled "Initialize to 0" must be written to zero during initialization. Failure to do so may result in a higher than normal operating
current.

Byte 0:

Active/inactive register

1 = enable; 0 = disable

BIT

PIN#

NAME

INITIAL VALUE

DESCRIPTION

2, 3

CLK0, CLK0

Enable/Disable Outputs

5, 6

CLK1, CLK1

Enable/Disable Outputs

9, 10

CLK2, CLK2

Enable/Disable Outputs

19, 20

CLK3, CLK3

Enable/Disable Outputs

22, 23

CLK4, CLK4

Enable/Disable Outputs

47, 46

CLK5, CLK5

Enable/Disable Outputs

44, 43

CLK6, CLK6

Enable/Disable Outputs

40, 39

CLK7, CLK7

Enable/Disable Outputs

NOTE:
1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be

configured during the normal modes of operation.

Byte 1:

Active/inactive register

1 = enable; 0 = disable

BIT

PIN#

NAME

INITIAL VALUE

DESCRIPTION

30, 29

CLK8, CLK8

Enable/Disable Outputs

27, 26

CLK9, CLK9

Enable/Disable Outputs

Reserved

Power-Down Mode Disable/Enable

HCSL Enable/Disable

NOTE:
1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be

configured during the normal modes of operation.

Philips Semiconductors

Product data

PCK2057

70 190 MHz I

C differential 1:10 clock driver

2001 Jun 12

ABSOLUTE MAXIMUM RATINGS (see Note 1)

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

DDQ

/AV

Supply voltage range

0.5

3.6

C supply voltage range

0.5

4.6

Input voltage range

except SCL and SDA

see Notes 2 and 3

0.5

DDQ

+ 0.5

Input voltage range

SCL and SDA

see Notes 2 and 3

0.5

C + 0.5

Output voltage range

see Notes 2 and 3

0.5

DDQ

+ 0.5

Input clamp current

< 0 or V

> V

DDQ

Output clamp current

< 0 or V

> V

DDQ

Continuous output current

= 0 to V

DDQ

Continuous current to GND or V

DDQ

100

stg

Storage temperature range

+150

NOTES:

1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 3.6 V maximum.

RECOMMENDED OPERATING CONDITIONS (see Note 1)

SYMBOL

PARAMETER

TEST

LIMITS

UNIT

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

DDQ

2.3

2.7

Supply voltage

2.2

2.7

see Note 2

2.3

3.6

CLK, CLK,
HCSL buffer only

0.24

LOW-level input voltage

CLK, CLK

0.3

DDQ

0.4

FBIN, FBIN

DDQ

/2 0.18

SDA, SCL

0.3

CLK, CLK,
HCSL buffer only

0.66

0.71

HIGH-level input voltage

CLK, CLK

0.4

DDQ

+ 0.3

FBIN, FBIN

DDQ

/2 + 0.18

SDA, SCL

0.7

DC input signal voltage

see Note 3

0.3

DDQ

+ 0.3

Differential input signal

DC: CLK, FBIN

see Note 4

0.36

DDQ

+ 0.6

voltage

AC: CLK, FBIN

see Note 4

0.2

DDQ

+ 0.6

Input differential pair cross-voltage

see Note 5

0.45

)

0.55

)

HIGH-level output current

LOW level output current

LOW-level output current

SDA

Input slew rate

see Figure 3

V/ns

SSC modulation frequency

33.3

kHz

SSC clock input frequency deviation

0.50

amb

Operating free-air temperature

+70

NOTES:
1. Unused inputs must be held HIGH or LOW to prevent them from floating.

2. All devices on the I

C-bus, with input levels related to V

C, must have one common supply line to which the pull-up resistor is connected.

3. DC input signal voltage specifies the allowable DC execution of differential input.

4. Differential input signal voltage specifies the differential voltage |V

| required for switching, where V

is the true input level, and V

is the complementary input level.

5. Differential cross-point voltage is expected to track variations of V

and is the voltage at which the differential signals must be crossing.

Philips Semiconductors

Product data

PCK2057

70 190 MHz I

C differential 1:10 clock driver

2001 Jun 12

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input voltage

All inputs

DDQ

= 2.3 V; I

= 18 mA

1.2

HIGH level output voltage

DDQ

= min to max; I

= 1 mA

DDQ

0.1

HIGH-level output voltage

DDQ

= 2.3 V; I

= 12 mA

1.7

LOW level output voltage

DDQ

= min to max; I

= 1 mA

0.1

LOW-level output voltage

DDQ

= 2.3 V; I

= 12 mA

0.6

SDA

C = 3.0 V; I

= 3 mA

0.4

Output differential cross voltage

DDQ

/2 0.2

DDQ

/2 + 0.2

Input current

CLK, FBIN

DDQ

= 2.7 V; V

= 0 V to 2.7 V

High impedance state output current

DDQ

= 2.7 V; V

= V

DDQ

or GND

Power-down current on V

DDQ

+ AV

CLK at 0 MHz;

of I

and AI

150

250

DDPD

Power-down current on V

CLK at 0 MHz; V

DDQ

= 3.6 V

Dynamic current on V

DDQ

= 100 MHz

205

230

Supply current on AV

= 100 MHz

Supply current on V

C = 3.6 V;

SCL and SDA = 3.6V

Input capacitance

DDQ

= 2.5 V; V

= V

DDQ

or GND

2.8

NOTES:
1. All typical values are at respective nominal V

DDQ

TIMING REQUIREMENTS

Over recommended ranges of supply voltage and operating free-air temperature.

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

MIN

MAX

UNIT

CLK

Clock frequency

190

MHz

Input clock duty cycle

Stabilization time

100

NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,

a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input
modulation under SSC application.

TIMING REQUIREMENTS FOR THE I

C INTERFACE

Over recommended ranges of operating free-air temperature and V

C from 3.3 V to 3.6 V..

SYMBOL

PARAMETER

STANDARD-MODE I

C-BUS

UNIT

SYMBOL

PARAMETER

MIN

MAX

UNIT

SCL

SCL clock frequency

100

kHz

BUF

Bus free time between a STOP and START condition

4.7

SU;STA

Set-up time for a repeated START condition

4.7

HD;STA

Hold time (repeated) START condition. After this period, the first clock is generated.

4.0

LOW

LOW period of the SCL clock

4.7

HIGH

HIGH period of the SCL clock

4.0

Rise time of both SDA and SCL signals

1000

Fall time of both SDA and SCL signals

300

SU;DAT

DATA set-up time

250

HD;DAT

DATA hold time

SU;STO

Set-up time for STOP condition

Philips Semiconductors

Product data

PCK2057

70 190 MHz I

C differential 1:10 clock driver

2001 Jun 12

AC CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay time

Test mode/CLK to any output

3.7

PHL

HIGH-to-LOW level propagation delay time

SCL to SDA (acknowledge)

500

Output enable time

Test mode/SDA to Y output

dis

Output disable time

Test mode/SDA to Y output

jit(per)

Jitter (period); see Figure 4

100 MHz to 167 MHz

jit(cc)

Jitter (cycle-to-cycle); see Figure 5

100 MHz to 167 MHz

jit(hper)

Half-period jitter; see Figure 6

100 MHz to 167 MHz

Static phase offset; see Figure 1

133 MHz/V

on CLK = 0.71 V

220

450

Static phase offset; see Figure 1

167 MHz/V

on CLK = 0.71 V

140

270

slr(o)

Output clock slew rate; see Figure 3

terminated with 120

/14 pF

V/ns

sk(o)

Output skew; see Figure 2

SSC modulation frequency

33.3

kHz

SSC clock input frequency deviation

0.00

0.50

NOTE:
1. This time is for a PLL frequency of 100 MHz.

AC WAVEFORMS

SW00882

(O)

n =N

(O)n

(O)n + 1

(N is a large number of samples)

CLK

Figure 1. Static phase offset

SW00883

sk(O)

Yx, FB

OUT

Yx, FB

OUT

Figure 2. Output skew

Philips Semiconductors

Product data

PCK2057

70 190 MHz I

C differential 1:10 clock driver

2001 Jun 12

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 06-01

Document order number:

9397 750 08476

Philips

Semiconductors

Data sheet status

[1]

Objective data

Preliminary data

Product data

Product
status

[2]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.

Data sheet status

[1] Please consult the most recently issued datasheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

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