Philips
Semiconductors
PCK2510S
50150 MHz 1:10 SDRAM clock driver
Product specification
1999 Dec 13
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
PCK2510S
50150 MHz 1:10 SDRAM clock driver
2
1999 Dec 13
8532184 22832
FEATURES
Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM
applications
Spread Spectrum clock compatible
Operating frequency 50 to 150 MHz
(t
phase
error
jitter) at 100 to133 MHz =
50 ps
Jitter (peak-peak) at 100 to 133 MHz =
80 ps
Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
Pin-to-pin skew
<
200 ps
Available in plastic 24-Pin TSSOP
Distributes one clock input to one bank of ten outputs
External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
On-Chip series damping resistors
No external RC network required
Operates at 3.3 V
DESCRIPTION
The PCK2510S is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLL to precisely
align, in both frequency and phase, the feedback (FBOUT) output to
the clock (CLK) input signal. It is specifically designed for use with
synchronous DRAMs. The PCK2510S operates at 3.3 V V
CC
and is
input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series damping resistors that make it ideal
for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of
CLK. Output signal duty cycles are adjusted to 50 percent,
independent of the duty cycle at CLK. All outputs can be enabled or
disabled via a single output enable input. When the G input is high,
the outputs switch in phase and frequency with CLK; when the G
input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the PCK2510S does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2510S requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power
up and application of a fixed-frequency, fixed-phase signal at CLK,
and following any changes to the PLL reference. The PLL can be
bypassed for test purposes by strapping AV
CC
to ground.
The PCK2510S is characterized for operation from 0
C to +70
C.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AGND
CLK
AV
CC
V
CC
V
CC
1Y9
1Y0
1Y8
GND
1Y1
GND
1Y6
1Y2
1Y7
1Y5
GND
V
CC
FBIN
GND
1Y3
1Y4
SW00382
V
CC
G
FBOUT
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
24-Pin Plastic TSSOP
0
C to +70
C
PCK2510S PW
SOT355-1
Philips Semiconductors
Product specification
PCK2510S
50150 MHz 1:10 SDRAM clock driver
1999 Dec 13
3
PIN DESCRIPTIONS
PIN NUMBER
SYMBOL
TYPE
NAME, FUNCTION, and DIRECTION
1
AGND
GND
Analog ground. AGND provides the ground reference for the analog circuitry.
2, 10, 14, 22
V
CC
PWR
Power supply
3, 4, 5, 8, 9,
15, 16, 17, 20, 21
1Y (09)
OUT
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y (09) is enabled
via the G input. These outputs can be disabled to a logic-low state by de-asserting the G control
input. Each output has an integrated 25
series-damping resistor.
6, 7, 18, 19
GND
GND
Ground
11
G
IN
Output bank enable. G is the output enable for outputs 1Y (09). When G is LOW, outputs 1Y
(09) are disabled to a logic LOW state. When G is HIGH, all outputs 1Y (09) are enabled and
switch at the same frequency as CLK.
12
FBOUT
OUT
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency
as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
FBOUT has an integrated 25
series-damping resistor.
13
FBIN
IN
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be
hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so
that there is nominally zero phase error between CLK and FBIN.
23
AV
CC
PWR
Analog power supply. AV
CC
provides the power reference for the analog circuitry. In addition,
AV
CC
can be used to bypass the PLL for test purposes. When AV
CC
is strapped to ground, PLL
is bypassed and CLK is buffered directly to the device outputs.
24
CLK
IN
Clock input. CLK provides the clock signal to be distributed by the PCK2510S clock driver. CLK
is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock.
Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required
for the PLL to phase lock the feedback signal to its reference signal.
FUNCTION TABLE
INPUTS
OUTPUTS
G
CLK
1Y (09)
FBOUT
X
L
L
L
L
H
L
H
H
H
H
H
Philips Semiconductors
Product specification
PCK2510S
50150 MHz 1:10 SDRAM clock driver
1999 Dec 13
4
FUNCTIONAL BLOCK DIAGRAM
SW00383
FBOUT
AV
CC
FBIN
CLK
G
11
24
13
23
PLL
1Y9
1Y8
1Y7
1Y6
1Y5
1Y4
1Y3
1Y2
1Y1
1Y0
3
4
5
8
9
15
16
17
20
21
12
ABSOLUTE MAXIMUM RATINGS
1, 3
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITION
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
AV
CC
Supply voltage range
Note 2
< V
CC
+ 0.7
V
V
CC
Supply voltage range
0.5
+4.6
V
I
IK
Input clamp current
V
I
< 0
50
mA
V
I
Input voltage range
Note 3
0.5
6.5
V
I
OK
Output clamp current
V
O
> V
CC
or V
O
< 0
50
mA
V
O
Output voltage range
Notes 3, 4
0.5
V
CC
+ 0.5
V
I
O
DC output source or sink current
V
O
= 0 to V
CC
50
mA
T
STG
Storage temperature range
65
+150
C
P
TOT
Power dissipation per package
700
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. AV
CC
must not exceed V
CC
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4. This value is limited to 4.6 V maximum.
Philips Semiconductors
Product specification
PCK2510S
50150 MHz 1:10 SDRAM clock driver
1999 Dec 13
5
RECOMMENDED OPERATING CONDITIONS
1
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
, AV
CC
Supply voltage
3
3.6
V
V
IH
HIGH level input voltage
2
V
V
IL
LOW level input voltage
0
0.8
V
V
I
Input voltage
0
V
CC
V
T
amb
Operating ambient temperature range in free air
0
+70
C
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
AV
CC
, V
CC
(V)
OTHER
MIN
TYP
MAX
UNIT
V
IK
Input clamp voltage
3
I
I
= 18 mA
1.2
V
MIN to MAX
I
OH
= 100
A
V
CC
0.2
V
OH
HIGH level output voltage
3
I
OH
= 12 mA
2.1
V
3
I
OH
= 6 mA
2.4
MIN to MAX
I
OL
= 100
A
0.2
V
OL
LOW level output voltage
3
I
OL
= 12 mA
0.8
V
3
I
OL
= 6 mA
0.55
I
I
Input current
3.6
V
I
= V
CC
or GND
5
A
I
CC
Quiescent supply current
3.6
V
I
= V
CC
or GND;
I
O
= 0, outputs: LOW or HIGH
10
A
I
CCA
AV
CC
power supply current
AV
CC
= 3.3
30
50
A
I
CC
Additional supply current per
input pin
3.3 to 3.6
One input at V
CC
0.6 V;
other inputs at V
CC
or GND
500
A
C
I
Input capacitance
3.3
V
I
= V
CC
or GND
2.8
pF
C
O
Output capacitance
3.3
V
O
= V
CC
or GND
5.4
pF
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature
SYMBOL
PARAMETER
MIN
MAX
UNIT
f
CLK
Clock frequency
50
150
MHz
Input clock duty cycle
40
60
%
Stabilization time
1
1
ms
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
Philips Semiconductors
Product specification
PCK2510S
50150 MHz 1:10 SDRAM clock driver
1999 Dec 13
6
SWITCHING CHARACTERISTICS
Over recommended ranges of supply voltage and operating free-air temperature; C
L
= 30 pF
1
PARAMETER
FROM
TO
V
CC
, AV
CC
= 3.3 V
0.3 V
UNIT
PARAMETER
(INPUT)/CONDITION
(OUTPUT)
MIN
TYP
MAX
UNIT
t
2
CLKIN
= 100 MHz to 133 MHz
FBIN
100
100
ps
t
phase error
2
CLKIN
= 66 MHz
FBIN
125
125
ps
t
phase error
jitter
3
CLKIN
= 100 MHz to 133 MHz
FBIN
50
50
ps
t
SK(0)
Any Y or FBOUT
Any Y or FBOUT
200
ps
jitter
(peak-peak)
CLKIN = 100 MHz to 133 MHz
Any Y or FBOUT
80
80
ps
jitter
(cycle-cycle)
CLKIN = 100 MHz to 133 MHz
Any Y or FBOUT
|65|
ps
Duty cycle reference
F(CLKIN
>
60 MHz)
Any Y or FBOUT
47
53
%
t
r
V
O
= 0.4 V to 2 V
Any Y or FBOUT
2.5
1
V/ns
t
f
V
O
= 0.4 V to 2 V
Any Y or FBOUT
2.5
1
V/ns
NOTES:
1. These parameters are not production tested.
2. This is considered as static phase error.
3. Phase error does not include jitter. (t
phase error
= static phase error jitter
(cycle-cycle)
)
4. The t
SK(0)
specification is only valid for equal loading of all outputs.
PARAMETER MEASUREMENT INFORMATION
SW00384
3V
0V
V
OH
V
OL
OUTPUT
INPUT
50% V
CC
50% V
CC
t
f
t
r
2V
0.4V
2V
0.4V
FROM OUTPUT
UNDER TEST
30pF
500
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS & PHASE ERROR TIMES
NOTES:
1. C
L
includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR
100MHz, Z
O
= 50
, t
r
1.2ns, t
f
1.2ns.
3. The outputs are measured one at a time with one transition per measurement.
t
pe
Figure 1. Load Circuit and Voltage Waveforms
Philips Semiconductors
Product specification
PCK2510S
50150 MHz 1:10 SDRAM clock driver
1999 Dec 13
7
FBIN
CLKIN
t
phase error
FBOUT
ANY Y
t
SK(0)
ANY Y
ANY Y
t
SK(0)
SW00385
Figure 2. Phase Error and Skew Calculations
Philips Semiconductors
Product specification
PCK2510S
50100 MHz 1:10 SDRAM clock driver
1999 Dec 13
8
TSSOP24:
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
Philips Semiconductors
Product specification
PCK2510S
50100 MHz 1:10 SDRAM clock driver
1999 Dec 13
9
NOTES
Philips Semiconductors
Product specification
PCK2510S
50100 MHz 1:10 SDRAM clock driver
1999 Dec 13
10
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Date of release: 12-99
Document order number:
9397 750 06707
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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