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Электронный компонент: PHB11N06LT

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Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB11N06LT, PHD11N06LT
Logic level FET
FEATURES
SYMBOL
QUICK REFERENCE DATA
'Trench' technology
V
DSS
= 55 V
Very low on-state resistance
Fast switching
I
D
= 11 A
Stable off-state characteristics
High thermal cycling performance
R
DS(ON)
150 m
(V
GS
= 5 V)
Low thermal resistance
R
DS(ON)
130 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHB11N06LT is supplied in the SOT404 surface mounting package.
The PHD11N06LT is supplied in the SOT428 surface mounting package.
PINNING
SOT428
SOT404
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 175C
-
55
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 175C; R
GS
= 20 k
-
55
V
V
GS
Gate-source voltage
-
13
V
I
D
Continuous drain current
T
mb
= 25 C
-
11
A
T
mb
= 100 C
-
7.6
A
I
DM
Pulsed drain current
T
mb
= 25 C
-
44
A
P
D
Total power dissipation
T
mb
= 25 C
-
36
W
T
j
, T
stg
Operating junction and
- 55
175
C
storage temperature
d
g
s
1
3
tab
2
1
2
3
tab
1 It is not possible to make contact to pin 2 of the SOT404 or SOT428 package
September 1998
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB11N06LT, PHD11N06LT
Logic level FET
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
C
Electrostatic discharge
Human body model (100 pF, 1.5 k
)
-
2
kV
capacitor voltage, all pins
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-mb
Thermal resistance junction
-
4.17
K/W
to mounting base
R
th j-a
Thermal resistance junction
SOT78 package, in free air
60
-
K/W
to ambient
SOT428 and SOT404 package, pcb
50
-
K/W
mounted, minimum footprint
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
55
-
-
V
voltage
T
j
= -55C
50
-
-
V
V
(BR)GSS
Gate-source breakdown
I
G
=
1 mA;
10
-
-
V
voltage
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1.0
1.5
2.0
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
-
2.3
V
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 5.5 A
-
100
130
m
resistance
V
GS
= 5 V; I
D
= 5.5 A
-
120
150
m
T
j
= 175C
-
250
315
m
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 5.5 A
4
10
-
S
I
GSS
Gate source leakage current V
GS
=
5 V; V
DS
= 0 V
-
0.02
1
A
T
j
= 175C
-
-
20
A
I
DSS
Zero gate voltage drain
V
DS
= 55 V; V
GS
= 0 V;
-
0.05
10
A
current
T
j
= 175C
-
-
500
A
Q
g(tot)
Total gate charge
I
D
= 11 A; V
DD
= 44 V; V
GS
= 5 V
-
6.1
-
nC
Q
gs
Gate-source charge
-
1.3
-
nC
Q
gd
Gate-drain (Miller) charge
-
3.2
-
nC
t
d on
Turn-on delay time
V
DD
= 30 V; I
D
= 5 A;
-
6
16
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
G
= 10
-
23
35
ns
t
d off
Turn-off delay time
Resistive load
-
18
30
ns
t
f
Turn-off fall time
-
18
30
ns
L
d
Internal drain inductance
Measured from tab to centre of die
-
3.5
-
nH
L
s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
250
330
pF
C
oss
Output capacitance
-
34
50
pF
C
rss
Feedback capacitance
-
35
50
pF
September 1998
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB11N06LT, PHD11N06LT
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
-
-
11
A
(body diode)
I
SM
Pulsed source current (body
-
-
44
A
diode)
V
SD
Diode forward voltage
I
F
= 11 A; V
GS
= 0 V
-
0.95
1.2
V
t
rr
Reverse recovery time
I
F
= 11 A; -dI
F
/dt = 100 A/
s;
-
34
-
ns
Q
rr
Reverse recovery charge
V
GS
= 0 V; V
R
= 30 V
-
57
-
nC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
10 A; V
DD
25 V; V
GS
= 5 V;
-
10
mJ
unclamped inductive turn-off
R
GS
= 50
; T
mb
= 25 C
energy
September 1998
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB11N06LT, PHD11N06LT
Logic level FET
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1us
10us
100us
1ms
10ms
0.1s
1s
10s
0.001
0.01
0.1
1
10
PHB11N06LT
pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
D =
t
p
t
p
T
T
P
t
D
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
0
2
4
6
8
10
PHB11N06LT
VDS, Drain-Source voltage (Volts)
ID, Drain current (Amps)
VGS = 2.6 V
2.8 V
3 V
3.2 V
3.4 V
3.6 V
5 V
10 V
Tj = 25 C
1
10
100
0.1
1
10
100
DC
PHB11N06LT
VDS, Drain-source voltage (Volts)
ID, Drain current (Amps)
RDS(ON) = VDS/ID
100 us
1 ms
10 ms
10 us
tp =
0
2
4
6
8
10
0
0.1
0.2
0.3
0.4
0.5
VGS = 5 V
PHB11N06LT
ID, Drain current (Amps)
RDS(on), Drain-Source on resistance (Ohms)
10 V
2.6V
2.8V
3V
3.2V
3.4V
3.6V
Tj = 25 C
September 1998
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB11N06LT, PHD11N06LT
Logic level FET
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 5.5 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
1
2
3
4
5
0
2
4
6
8
10
PHB11N06LT
Gate-source voltage, VGS (V)
Drain current, ID (A)
Tj = 25 C
175 C
VDS > ID x RDS(on)
BUK959-60
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
2
4
6
8
10
0
1
2
3
4
5
6
7
8
PHB11N06LT
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
Tj = 175 C
VDS > ID x RDS(on)
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
-100
-50
0
50
100
150
200
0.5
1
1.5
2
2.5
BUK959-60
Tmb / degC
Rds(on) normlised to 25degC
a
0.1
1
10
100
10
100
1000
PHB11N06LT
Drain-source voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
September 1998
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB11N06LT, PHD11N06LT
Logic level FET
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
)
Fig.16. Avalanche energy test circuit.
0
2
4
6
8
10
12
0
5
10
15
PHB11N06LT
Qg, Gate charge (nC)
VGS, Gate-Source voltage (Volts)
VDD = 44 V
ID = 11 A
Tj = 25 C
20
40
60
80
100
120
140
160
180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
5
10
15
20
PHB11N06LT
VGS = 0V
Source-drain voltage, VSDS (V)
Source-drain diode current, IF (A)
Tj = 25 C
175 C
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
September 1998
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB11N06LT, PHD11N06LT
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
Fig.17. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.18. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
11 max
4.5 max
1.4 max
10.3 max
0.5
15.4
2.5
0.85 max
(x2)
2.54 (x2)
17.5
11.5
9.0
5.08
3.8
2.0
September 1998
7
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB11N06LT, PHD11N06LT
Logic level FET
MECHANICAL DATA
Dimensions in mm : Net Mass: 1.4 g
Fig.19. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.20. SOT428 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
6.22 max
2.38 max
0.93 max
6.73 max
0.3
10.4 max
0.5
0.8 max
(x2)
2.285 (x2)
0.5
seating plane
1.1
0.5 min
5.4
4 min
4.6
1
2
3
tab
7.0
7.0
2.15
2.5
4.57
1.5
September 1998
8
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB11N06LT, PHD11N06LT
Logic level FET
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
September 1998
9
Rev 1.000