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Электронный компонент: PHB45N03LT

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Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB45N03LT
Logic level FET
FEATURES
SYMBOL
QUICK REFERENCE DATA
'Trench' technology
V
DSS
= 30 V
Very low on-state resistance
Fast switching
I
D
= 45 A
Stable off-state characteristics
High thermal cycling performance
R
DS(ON)
24 m
(V
GS
= 5 V)
Low thermal resistance
Surface mounting package
R
DS(ON)
21 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
PINNING
SOT404
N-channel
enhancement
mode
PIN
DESCRIPTION
logic
level
field-effect
power
transistor in a plastic envelope
1
gate
using 'trench' technology. The
device
has
very
low
on-state
2
drain (no connection
resistance. It is intended for use in
possible)
dc to dc converters and general
purpose switching applications.
3
source
The PHB45N03LT is supplied in the
tab
drain
SOT404
surface
mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
-
30
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
30
V
V
GS
Gate-source voltage
-
-
15
V
I
D
Drain current (DC)
T
mb
= 25 C
-
45
A
I
D
Drain current (DC)
T
mb
= 100 C
-
36
A
I
DM
Drain current (pulse peak value)
T
mb
= 25 C
-
180
A
P
tot
Total power dissipation
T
mb
= 25 C
-
86
W
T
stg
, T
j
Storage & operating temperature
-
- 55
175
C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-mb
Thermal resistance junction to
-
-
1.75
K/W
mounting base
R
th j-a
Thermal resistance junction to
pcb mounted, minimum
50
-
K/W
ambient
footprint
d
g
s
1
3
mb
2
December 1997
1
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB45N03LT
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
30
-
-
V
voltage
T
j
= -55C
27
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1
1.5
2
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
-
2.3
I
DSS
Zero gate voltage drain current
V
DS
= 30 V; V
GS
= 0 V;
-
0.05
10
A
T
j
= 175C
-
-
500
A
I
GSS
Gate source leakage current
V
GS
=
5 V; V
DS
= 0 V
-
10
100
nA
R
DS(ON)
Drain-source on-state
V
GS
= 5 V; I
D
= 25 A
-
20
24
m
resistance
V
GS
= 10 V; I
D
= 25 A
-
16
21
m
V
GS
= 5 V; I
D
= 25 A; T
j
= 175C
-
-
45
m
DYNAMIC CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
8
16
-
S
Q
g(tot)
Total gate charge
I
D
= 40 A; V
DD
= 24 V; V
GS
= 5 V
-
23
-
nC
Q
gs
Gate-source charge
-
3
-
nC
Q
gd
Gate-drain (Miller) charge
-
9
-
nC
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
1050
-
pF
C
oss
Output capacitance
-
270
-
pF
C
rss
Feedback capacitance
-
140
-
pF
t
d on
Turn-on delay time
V
DD
= 15 V; I
D
= 25 A;
-
30
45
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
G
= 5
-
80
130
ns
t
d off
Turn-off delay time
Resistive load
-
95
135
ns
t
f
Turn-off fall time
-
40
55
ns
L
d
Internal drain inductance
Measured from tab to centre of die
-
3.5
-
nH
L
d
Internal drain inductance
Measured from drain lead solder
-
4.5
-
nH
point to centre of die
L
s
Internal source inductance
Measured from source lead solder
-
7.5
-
nH
point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
DR
Continuous reverse drain
-
-
45
A
current
I
DRM
Pulsed reverse drain current
-
-
180
A
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.95
1.2
V
I
F
= 40 A; V
GS
= 0 V
-
1.0
-
t
rr
Reverse recovery time
I
F
= 40 A; -dI
F
/dt = 100 A/
s;
-
52
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 25 V
-
0.08
-
C
December 1997
2
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB45N03LT
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 25 A; V
DD
25 V;
-
-
60
mJ
unclamped inductive turn-off
V
GS
= 10 V; R
GS
= 50
; T
mb
= 25 C
energy
December 1997
3
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB45N03LT
Logic level FET
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1E-07
1E-05
1E-03
1E-01
1E+01
0.01
0.1
1
10
7528-30
t / s
Zth j-mb / (K/W)
D =
t
p
t
p
T
T
P
t
D
D =
0
0.02
0.05
0.1
0.2
0.5
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
0
20
40
60
80
9528-30
VDS / V
ID / A
2.5
3
3.5
4
4.5
5
10
6
VGS / V =
1
10
100
1
10
100
1000
7528-30
VDS / V
ID / A
tp = 10 us
100 us
1 ms
10 ms
RDS(ON) = VDS / ID
DC
0
20
40
60
80
0
9528-30
ID / A
RDS(ON) / mOhm
VGS / V =
10
6
5
4.5
4
10
20
30
40
December 1997
4
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB45N03LT
Logic level FET
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
1
2
3
4
5
6
0
10
20
30
40
50
60
9528-30
VGS / V
ID / A
Tj / C = 25
175
BUK959-60
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
10
20
30
40
50
60
0
5
10
15
20
25
9528-30
ID / A
gfs / S
Tj / C = 25
175
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
-100
0
100
200
0
0.5
1
1.5
2
30V TrenchMOS
Tj / C
a
150
50
-50
0.1
1
10
100
100
1000
10000
9528-30
VDS / V
C / pF
Ciss
Coss
Crss
December 1997
5
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB45N03LT
Logic level FET
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 40 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 25 A
Fig.16. Avalanche energy test circuit.
Fig.17. Switching test circuit.
0
5
10
15
20
25
0
1
2
3
4
5
9528-30
QG / nC
VGS / V
VDS / V = 6
24
20
40
60
80
100
120
140
160
180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0
0.5
1
1.5
2
0
10
20
30
40
50
60
9528-30
VSDS / V
IF / A
Tj / C = 175
25
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
RD
T.U.T.
VDD
RG
VDS
+
-
VGS
0
December 1997
6
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB45N03LT
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
Fig.18. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.19. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
11 max
4.5 max
1.4 max
10.3 max
0.5
15.4
2.5
0.85 max
(x2)
2.54 (x2)
17.5
11.5
9.0
5.08
3.8
2.0
December 1997
7
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB45N03LT
Logic level FET
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
December 1997
8
Rev 1.300