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Электронный компонент: PHB69N03LT

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Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LT
Logic level FET
PHD69N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
'Trench' technology
V
DSS
= 25 V
Very low on-state resistance
Fast switching
I
D
= 69 A
Low thermal resistance
Logic level compatible
R
DS(ON)
12 m
(V
GS
= 10 V)
R
DS(ON)
14 m
(V
GS
= 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology.
Applications:-
 High frequency computer motherboard d.c. to d.c. converters
High current switching
The PHP69N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB69N03LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD69N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D
2
PAK)
SOT428 (DPAK)
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 175C
-
25
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 175C; R
GS
= 20 k
-
25
V
V
GS
Gate-source voltage (DC)
-
15
V
V
GSM
Gate-source voltage (pulse
T
j
150C
-
20
V
peak value)
I
D
Drain current (DC)
T
mb
= 25 C
-
69
A
T
mb
= 100 C
-
48
A
I
DM
Drain current (pulse peak
T
mb
= 25 C
-
240
A
value)
P
tot
Total power dissipation
T
mb
= 25 C
-
125
W
T
j
, T
stg
Operating junction and
- 55
175
C
storage temperature
d
g
s
1 2 3
tab
1
3
tab
2
1
2
3
tab
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction
-
-
1.2
K/W
to mounting base
R
th j-a
Thermal resistance junction
SOT78 package, in free air
-
60
-
K/W
to ambient
SOT404 and SOT428 packages, pcb
-
50
-
K/W
mounted, minimum footprint
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 25 A; V
DD
15 V;
-
60
mJ
unclamped inductive turn-off
V
GS
= 5 V; R
GS
= 50
; T
mb
= 25 C
energy
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
25
-
-
V
voltage
T
j
= -55C
22
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1
1.5
2
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
-
2.3
V
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 25 A
-
8.5
12
m
resistance
V
GS
= 5 V; I
D
= 25 A
-
11
14
m
V
GS
= 5 V; I
D
= 25 A; T
j
= 175C
-
-
26
m
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
12
40
-
S
I
GSS
Gate source leakage current V
GS
=
5 V; V
DS
= 0 V
-
10
100
nA
I
DSS
Zero gate voltage drain
V
DS
= 25 V; V
GS
= 0 V;
-
0.05
10
A
current
T
j
= 175C
-
-
500
A
Q
g(tot)
Total gate charge
I
D
= 69 A; V
DD
= 15 V; V
GS
= 5 V
-
26
-
nC
Q
gs
Gate-source charge
-
7.6
-
nC
Q
gd
Gate-drain (Miller) charge
-
11
-
nC
t
d on
Turn-on delay time
V
DD
= 15 V; I
D
= 25 A;
-
7
15
ns
t
r
Turn-on rise time
V
GS
= 10 V; R
G
= 5
-
50
75
ns
t
d off
Turn-off delay time
Resistive load
-
82
120
ns
t
f
Turn-off fall time
-
59
75
ns
L
d
Internal drain inductance
Measured tab to centre of die
-
3.5
-
nH
L
d
Internal drain inductance
Measured from drain lead to centre of die
-
4.5
-
nH
(SOT78 package only)
L
s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 20 V; f = 1 MHz
-
1700
-
pF
C
oss
Output capacitance
-
475
-
pF
C
rss
Feedback capacitance
-
300
-
pF
October 1999
2
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
-
-
69
A
(body diode)
I
SM
Pulsed source current (body
-
-
240
A
diode)
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.9
1.2
V
I
F
= 69 A; V
GS
= 0 V
-
1.0
-
t
rr
Reverse recovery time
I
F
= 20 A; -dI
F
/dt = 100 A/
s;
-
83
-
ns
Q
rr
Reverse recovery charge
V
GS
= 0 V; V
R
= 25 V
-
0.1
-
C
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); V
GS
5 V
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
1
10
100
1000
1
10
100
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
0.01
0.1
1
10
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
October 1999
3
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
0
5
10
15
20
25
30
35
40
45
50
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
2.2 V
2.4 V
Tj = 25 C
VGS = 10 V
2 V
2.6 V
4.5 V
2.8 V
3 V
5 V
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
175 C
VDS > ID X RDS(ON)
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0
5
10
15
20
25
30
35
40
45
50
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS =4.5 V
10V
Tj = 25 C
2.8V
3 V
2.6 V
2.2 V
2.4 V
5 V
Normalised On-state Resistance
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
Junction temperature, Tj (C)
0
5
10
15
20
25
30
35
40
45
50
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
175 C
Threshold Voltage, VGS(TO) (V)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
Junction Temperature, Tj (C)
typical
maximum
minimum
October 1999
4
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0
0.5
1
1.5
2
2.5
3
Gate-source voltage, VGS (V)
minimum
typical
maximum
VDS = 5 V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
5
10
15
20
25
30
35
40
45
50
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 69 A
Tj = 25 C
VDD = 15 V
100
1000
10000
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
0
5
10
15
20
25
30
35
40
45
50
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
175 C
VGS = 0 V
October 1999
5
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
MECHANICAL DATA
Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to mounting instructions for SOT78 (TO220AB) package.
3. Epoxy meets UL94 V0 at 1/8".
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT78
TO-220
D
D1
q
P
L
1
2
3
L2
(1)
b1
e
e
b
0
5
10 mm
scale
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
SOT78
DIMENSIONS (mm are the original dimensions)
A
E
A1
c
Note
1. Terminals in this zone are not tinned.
Q
L1
UNIT
A1
b1
D1
e
P
mm
2.54
q
Q
A
b
D
c
L2
(1)
max.
3.0
3.8
3.6
15.0
13.5
3.30
2.79
3.0
2.7
2.6
2.2
0.7
0.4
15.8
15.2
0.9
0.7
1.3
1.0
4.5
4.1
1.39
1.27
6.4
5.9
10.3
9.7
L1
E
L
97-06-11
October 1999
6
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
MECHANICAL DATA
Fig.16. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
A1
D1
D
max.
E
e
Lp
HD
Q
c
2.54
2.60
2.20
15.40
14.80
2.90
2.10
11
1.60
1.20
10.30
9.70
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
b
DIMENSIONS (mm are the original dimensions)
SOT404
0
2.5
5 mm
scale
Plastic single-ended surface mounted package (Philips version of D
2
-PAK); 3 leads
(one lead cropped)
SOT404
e
e
E
b
D1
HD
D
Q
Lp
c
A1
A
1
3
2
mounting
base
98-12-14
99-06-25
October 1999
7
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.17. SOT404 : soldering pattern for surface mounting.
17.5
11.5
9.0
5.08
3.8
2.0
October 1999
8
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
MECHANICAL DATA
Fig.18. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT428
98-04-07
0
10
20 mm
scale
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
E
b2
D1
w
A
M
b
c
b1
L1
L
1
3
2
D
E1
HE
L2
Note
1. Measured from heatsink back to lead.
e1
e
A
A2
A
A1
y
seating plane
mounting
base
A1
(1)
D
max.
b
D1
max.
E
max.
HE
max.
w
y
max.
A2
b2
b1
max.
c
E1
min.
e
e1
L1
min.
L2
L
A
max.
UNIT
DIMENSIONS (mm are the original dimensions)
0.2
0.2
mm
2.38
2.22
0.65
0.45
0.89
0.71
0.89
0.71
1.1
0.9
5.36
5.26
0.4
0.2
6.22
5.98
4.81
4.45
2.285
4.57
10.4
9.6
0.5
0.7
0.5
6.73
6.47
4.0
2.95
2.55
October 1999
9
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.19. SOT428 : soldering pattern for surface mounting.
7.0
7.0
2.15
2.5
4.57
1.5
October 1999
10
Rev 1.600
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP69N03LT, PHB69N03LTT
Logic level FET
PHD69N03LT
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
October 1999
11
Rev 1.600