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Электронный компонент: PHB80N06LT

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Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB80N06LT
Logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
SYMBOL
PARAMETER
MAX.
UNIT
level field-effect power transistor in a
plastic envelope suitable for surface
V
DS
Drain-source voltage
55
V
mounting. Using 'trench' technology
I
D
Drain current (DC)
1
75
A
the device features very low on-state
P
tot
Total power dissipation
178
W
resistance and has integral zener
T
j
Junction temperature
175
C
diodes giving ESD protection up to
R
DS(ON)
Drain-source on-state
14
m
2kV. It is intended for use in DC-DC
resistance
V
GS
= 5 V
converters and general purpose
switching applications.
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
mb
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
-
55
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
55
V
V
GS
Gate-source voltage
-
-
10
V
I
D
Drain current (DC)
1
T
mb
= 25 C
-
75
A
I
D
Drain current (DC)
T
mb
= 100 C
-
56
A
I
DM
Drain current (pulse peak value)
T
mb
= 25 C
-
240
A
P
tot
Total power dissipation
T
mb
= 25 C
-
178
W
T
stg
, T
j
Storage & operating temperature
-
- 55
175
C
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
C
Electrostatic discharge capacitor
Human body model
-
2
kV
voltage
(100 pF, 1.5 k
)
d
g
s
1
3
mb
2
1 Current limited by package to 75A from a theoretical value of 80A.
December 1997
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB80N06LT
Logic level FET
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-mb
Thermal resistance junction to
-
-
0.84
K/W
mounting base
R
th j-a
Thermal resistance junction to
Minimum footprint, FR4
50
-
K/W
ambient
board
STATIC CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
55
-
-
V
voltage
T
j
= -55C
50
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1.0
1.5
2.0
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
-
2.3
V
I
DSS
Zero gate voltage drain current
V
DS
= 55 V; V
GS
= 0 V;
-
0.05
10
A
T
j
= 175C
-
-
500
uA
I
GSS
Gate source leakage current
V
GS
=
5 V; V
DS
= 0 V
-
0.02
1
A
T
j
= 175C
-
-
10
A
V
(BR)GSS
Gate-source breakdown
I
G
=
1 mA;
10
-
-
V
voltage
R
DS(ON)
Drain-source on-state
V
GS
= 5 V; I
D
= 25 A
-
12
14
m
resistance
T
j
= 175C
-
-
30
m
DYNAMIC CHARACTERISTICS
T
mb
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
30
65
-
S
Q
g(tot)
Total gate charge
I
D
= 50 A; V
DD
= 44 V; V
GS
= 5 V
-
43
-
nC
Q
gs
Gate-source charge
-
13
-
nC
Q
gd
Gate-drain (Miller) charge
-
20
-
nC
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
2900
3800
pF
C
oss
Output capacitance
-
500
600
pF
C
rss
Feedback capacitance
-
240
330
pF
t
d on
Turn-on delay time
V
DD
= 30 V; I
D
= 25 A;
-
35
50
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
G
= 10
-
95
145
ns
t
d off
Turn-off delay time
-
130
180
ns
t
f
Turn-off fall time
-
60
80
ns
L
d
Internal drain inductance
Measured from upper edge of drain
-
2.5
-
nH
tab to centre of die
L
s
Internal source inductance
Measured from source lead
-
7.5
-
nH
soldering point to source bond pad
December 1997
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB80N06LT
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
DR
Continuous reverse drain
-
-
68
A
current
I
DRM
Pulsed reverse drain current
-
-
240
A
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.95
1.2
V
I
F
= 65 A; V
GS
= 0 V
-
1.0
-
V
t
rr
Reverse recovery time
I
F
= 65 A; -dI
F
/dt = 100 A/
s;
-
57
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 30 V
-
0.14
-
C
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 65 A; V
DD
25 V;
-
-
200
mJ
unclamped inductive turn-off
V
GS
= 5 V; R
GS
= 50
; T
mb
= 25 C
energy
December 1997
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB80N06LT
Logic level FET
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1E-07
1E-05
1E-03
1E-01
1E+01
t / s
Zth / (K/W)
1E+01
1E+00
1E-01
1E-02
1E-03
0
0.5
0.2
0.1
0.05
0.02
BUKX514-55
D =
t
p
t
p
T
T
P
t
D
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID (A)
Current Derating
100
80
60
40
20
0
Limited by package
0
2
4
6
8
10
0
20
40
60
80
100
ID/A
VDS/V
10
5
4
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
VGS/V =
VDS / V
ID / A
1 us
10 us
100 us
1 ms
10 ms
100 ms
tp =
1
10
100
1000
1
10
55
RDS(ON) = VDS/ID
DC
SOAX514
100
10
12
14
16
18
20
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95 100
RDS(ON)/mOhm
VGS/V =
3.6
4
4.2
4.4
4.6
5
ID/A
December 1997
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB80N06LT
Logic level FET
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
1
2
3
4
5
0
20
40
60
80
100
ID/A
VGS/V
Tj/C = 175
25
BUK959-60
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
20
40
60
80
100
0
10
20
30
40
50
60
70
gfs/S
ID/A
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
-100
-50
0
50
100
150
200
0.5
1
1.5
2
2.5
BUK959-60
Tmb / degC
Rds(on) normlised to 25degC
a
0.01
0.1
1
10
100
0
1
2
3
4
5
6
Thousands pF
Ciss
Coss
Crss
VDS/V
December 1997
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB80N06LT
Logic level FET
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 50 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 75 A
Fig.16. Avalanche energy test circuit.
Fig.17. Switching test circuit.
0
10
20
30
40
50
0
1
2
3
4
5
6
VGS/V
VDS = 14V
VDS = 44V
QG/nC
20
40
60
80
100
120
140
160
180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
20
40
60
80
100
IF/A
VSDS/V
Tj/C =
175
25
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
RD
T.U.T.
VDD
RG
VDS
+
-
VGS
0
December 1997
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB80N06LT
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
Fig.18. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.19. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
11 max
4.5 max
1.4 max
10.3 max
0.5
15.4
2.5
0.85 max
(x2)
2.54 (x2)
17.5
11.5
9.0
5.08
3.8
2.0
December 1997
7
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHB80N06LT
Logic level FET
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
December 1997
8
Rev 1.100