PHP/PHB/PHD108NQ03LT
TrenchMOSTM logic level FET
Rev. 02 -- 11 September 2002
Product data
1.
Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOSTM technology.
Product availability:
PHP108NQ03LT in SOT78 (TO-220AB)
PHB108NQ03LT in SOT404 (D
2
-PAK)
PHD108NQ03LT in SOT428 (D-PAK).
1.2 Features
1.3 Applications
1.4 Quick reference data
2.
Pinning information
[1]
It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
s
Logic level compatible
s
Very low on-state resistance
s
DC to DC converters
s
Switched mode power supplies
s
V
DS
= 25 V
s
I
D
= 75 A
s
P
tot
= 180 W
s
R
DSon
6 m
Table 1:
Pinning - SOT78, SOT404, SOT428, simplified outline and symbol
Pin
Description
Simplified outline
Symbol
1
gate (g)
SOT78 (TO-220AB)
SOT404 (D
2
-PAK)
SOT428 (D-PAK)
2
drain (d)
[1]
3
source (s)
mb
mounting base,
connected to
drain (d)
MBK106
1 2
mb
3
1
3
2
MBK116
mb
MBK091
Top view
1
3
mb
2
s
d
g
MBB076
Philips Semiconductors
PHP/PHB/PHD108NQ03LT
TrenchMOSTM logic level FET
Product data
Rev. 02 -- 11 September 2002
2 of 14
9397 750 10159
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
3.
Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
V
DS
drain-source voltage (DC)
25
C
T
j
175
o
C
-
25
V
V
DGR
drain-gate voltage (DC)
25
C
T
j
175
o
C; R
GS
= 20 k
-
25
V
I
D
drain current (DC)
T
mb
= 25
C; V
GS
= 5 V;
Figure 2
and
3
-
75
A
T
mb
= 100
C; V
GS
= 5 V;
Figure 2
and
3
-
60
A
V
GS
gate-source voltage
-
20
V
I
DM
peak drain current
T
mb
= 25
C; pulsed; t
p
10
s;
Figure 3
-
108
A
P
tot
total power dissipation
T
mb
= 25
C;
Figure 1
-
180
W
T
stg
storage temperature
-
55
+175
C
T
j
junction temperature
-
55
+175
C
Source-drain diode
I
S
source (diode forward) current (DC)
T
mb
= 25
C
-
75
A
I
SM
peak source (diode forward) current T
mb
= 25
C; pulsed; t
p
10
s
-
108
A
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
unclamped inductive load; I
D
= 43 A;
t
p
= 0.25 ms; V
DD
15 V; R
GS
= 50
;
V
GS
= 10 V; starting T
j
= 25
C
-
180
mJ
Philips Semiconductors
PHP/PHB/PHD108NQ03LT
TrenchMOSTM logic level FET
Product data
Rev. 02 -- 11 September 2002
3 of 14
9397 750 10159
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
V
GS
5 V
Fig 1.
Normalized total power dissipation as a
function of mounting base temperature.
Fig 2.
Normalized continuous drain current as a
function of mounting base temperature.
T
mb
= 25
C; I
DM
is single pulse
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
03aa16
0
40
80
120
0
50
100
150
200
Tmb (
C)
Pder
(%)
03aa24
0
40
80
120
0
50
100
150
200
Tmb (
C)
Ider
(%)
P
der
P
tot
P
tot 25 C
(
)
-----------------------
100%
=
I
der
I
D
I
D 25 C
(
)
-------------------
100%
=
003aaa190
1
10
102
103
1
10
102
VDS (V)
ID
(A)
DC
100
s
10 ms
Limit RDSon = VDS / ID
1 ms
tp = 10
s
Philips Semiconductors
PHP/PHB/PHD108NQ03LT
TrenchMOSTM logic level FET
Product data
Rev. 02 -- 11 September 2002
4 of 14
9397 750 10159
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
4.
Thermal characteristics
4.1 Transient thermal impedance
Table 3:
Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
R
th(j-mb)
thermal resistance from junction to mounting base
Figure 4
-
-
0.8
K/W
R
th(j-a)
thermal resistance from junction to ambient
SOT78
vertical in still air
-
60
-
K/W
SOT428
SOT428 minimum footprint;
mounted on a PCB
-
75
-
K/W
SOT404 and SOT428
SOT404 minimum footprint;
mounted on a PCB
-
50
-
K/W
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration.
003aaa191
10-2
10-1
1
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Zth(j-mb)
(K/W)
single pulse
= 0.5
0.2
0.1
0.05
0.02
tp
tp
T
P
t
T
=
Philips Semiconductors
PHP/PHB/PHD108NQ03LT
TrenchMOSTM logic level FET
Product data
Rev. 02 -- 11 September 2002
5 of 14
9397 750 10159
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5.
Characteristics
Table 4:
Characteristics
T
j
= 25
C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 250
A; V
GS
= 0 V
T
j
= 25
C
25
-
-
V
T
j
=
-
55
C
22
-
-
V
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
1
-
2
V
I
DSS
drain-source leakage current
V
DS
= 25 V; V
GS
= 0 V
T
j
= 25
C
-
0.05
1
A
T
j
= 175
C
-
-
500
A
I
GSS
gate-source leakage current
V
GS
=
10 V; V
DS
= 0 V
-
0.02
100
nA
R
DSon
drain-source on-state resistance
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
C
-
6.2
7.5
m
T
j
= 175
C
-
10
14
m
V
GS
= 10 V; I
D
= 25 A
-
5.1
6.0
m
Dynamic characteristics
Q
g(tot)
total gate charge
I
D
= 40 A; V
DD
= 15 V; V
GS
= 5 V;
Figure 13
-
23
-
nC
Q
gs
gate-source charge
-
8.4
-
nC
Q
gd
gate-drain (Miller) charge
-
7.3
9.9
nC
C
iss
input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 11
-
1990 -
pF
C
oss
output capacitance
-
580
-
pF
C
rss
reverse transfer capacitance
-
230
-
pF
t
d(on)
turn-on delay time
V
DD
= 15 V; R
D
= 0.6
; V
GS
= 5 V; R
G
= 10
-
24
-
ns
t
r
rise time
-
102
-
ns
t
d(off)
turn-off delay time
-
53
-
ns
t
f
fall time
-
54
-
ns
Source-drain diode
V
SD
source-drain (diode forward) voltage I
S
= 25 A; V
GS
= 0 V;
Figure 12
-
0.9
1.2
V
t
rr
reverse recovery time
I
S
= 20 A; dI
S
/dt =
-
100 A/
s; V
GS
= 0 V;
V
DS
= 25 V
-
34
-
ns
Q
r
recovered charge
-
27
-
nC
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