Document Outline
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- PINNING - SOT428
- PIN CONFIGURATION
- SYMBOL
- LIMITING VALUES
- THERMAL RESISTANCES
- ELECTRICAL CHARACTERISTICS
- SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
- MECHANICAL DATA
- MOUNTING INSTRUCTIONS
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
Philips Semiconductors
Product specification
PowerMOS transistor
PHD3N20L
Logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
SYMBOL
PARAMETER
MAX.
UNIT
level field-effect power transistor in a
plastic envelope suitable for surface
V
DS
Drain-source voltage
200
V
mounting featuring high avalanche
I
D
Drain current (DC)
3.5
A
energy capability, stable blocking
P
tot
Total power dissipation
50
W
voltage, fast switching and high
R
DS(ON)
Drain-source on-state resistance
1.5
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general
purpose
switching
applications.
PINNING - SOT428
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
I
D
Continuous drain current
T
mb
= 25 C; V
GS
= 10 V
-
3.5
A
T
mb
= 100 C; V
GS
= 10 V
-
2.5
A
I
DM
Pulsed drain current
T
mb
= 25 C
-
14
A
P
D
Total dissipation
T
mb
= 25 C
-
50
W
P
D
/
T
mb
Linear derating factor
T
mb
> 25 C
-
0.33
W/K
V
GS
Gate-source voltage
-
15
V
V
GSM
Non-repetitive gate-source
t
p
50
s
-
20
V
voltage
E
AS
Single pulse avalanche
V
DD
50 V; starting T
j
= 25C; R
GS
= 50
;
-
25
mJ
energy
V
GS
= 5 V
I
AS
Peak avalanche current
V
DD
50 V; starting T
j
= 25C; R
GS
= 50
;
-
3.5
A
V
GS
= 5 V
T
j
, T
stg
Operating junction and
- 55
175
C
storage temperature range
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-mb
Thermal resistance junction to
-
3
K/W
mounting base
R
th j-a
Thermal resistance junction to
pcb mounted, minimum
50
-
K/W
ambient
footprint
1
2
3
tab
d
g
s
September 1997
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHD3N20L
Logic level FET
ELECTRICAL CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA
200
-
-
V
voltage
V
(BR)DSS
/
Drain-source breakdown
V
DS
= V
GS
; I
D
= 0.25 mA
-
0.25
-
V/K
T
j
voltage temperature coefficient
R
DS(ON)
Drain-source on resistance
V
GS
= 5 V; I
D
= 2 A
-
0.77
1.5
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 0.25 mA
1.0
1.5
2.0
V
g
fs
Forward transconductance
V
DS
= 50 V; I
D
= 2 A
0.8
3.0
-
S
I
DSS
Drain-source leakage current
V
DS
= 200 V; V
GS
= 0 V
-
0.1
25
A
V
DS
= 160 V; V
GS
= 0 V; T
j
= 150 C
-
1
250
A
I
GSS
Gate-source leakage current
V
GS
=
15 V; V
DS
= 0 V
-
10
100
nA
Q
g(tot)
Total gate charge
I
D
= 3.3 A; V
DD
= 160 V; V
GS
= 5 V
-
7.5
9
nC
Q
gs
Gate-source charge
-
1
3
nC
Q
gd
Gate-drain (Miller) charge
-
4
6
nC
t
d(on)
Turn-on delay time
V
DD
= 100 V; I
D
= 3.3 A;
-
8
-
ns
t
r
Turn-on rise time
R
G
= 24
; R
D
= 30
-
33
-
ns
t
d(off)
Turn-off delay time
-
40
-
ns
t
f
Turn-off fall time
-
36
-
ns
L
d
Internal drain inductance
Measured from tab to centre of die
-
3.5
-
nH
L
s
Internal source inductance
Measured from source lead solder
-
7.5
-
nH
point to source bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
270
-
pF
C
oss
Output capacitance
-
48
-
pF
C
rss
Feedback capacitance
-
17
-
pF
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
S
Continuous source current
T
mb
= 25C
-
-
3.5
A
(body diode)
I
SM
Pulsed source current (body
T
mb
= 25C
-
-
14
A
diode)
V
SD
Diode forward voltage
I
S
= 3.3 A; V
GS
= 0 V
-
-
1.5
V
t
rr
Reverse recovery time
I
S
= 3.3 A; V
GS
= 0 V;
-
90
-
ns
dI/dt = 100 A/
s
Q
rr
Reverse recovery charge
-
0.5
-
C
September 1997
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHD3N20L
Logic level FET
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance.
R
DS(ON)
= f(I
D
); parameter V
GS
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0
0.5
0.2
0.1
0.05
0.02
D =
t
p
t
p
T
T
P
t
D
1us
10us
1ms
0.1s
10s
tp, pulse widtht (s)
Zth j-mb, Transient Thermal Impedance (K/W)
10
1
0.1
0.01
1s
10ms
100us
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
0
1
2
3
4
5
6
7
8
PHP2N20L
VDS, Drain-Source voltage (Volts)
ID, Drain current (Amps)
Tj = 25 C
VGS = 2.5 V
3 V
3.5 V
4 V
5 V
10 V
1
10
100
1000
0.1
1
10
100
PHP2N20E
100 us
1 ms
10 ms
100 ms
tp = 10 us
DC
RDS(ON) = VDS/ID
VDS, Drain-source voltage (Volts)
ID, Drain current (Amps)
0
1
2
3
4
5
6
7
8
0
1
2
3
4
PHP2N20L
ID, Drain current (Amps)
RDS(on), Drain-Source on resistance (Ohms)
VGS = 10 V
Tj = 25 C
2.5 V
3 V
3.5 V
4 V
5 V
September 1997
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHD3N20L
Logic level FET
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
Fig.8. Typical transconductance.
g
fs
= f(I
D
); parameter T
j
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 3.3 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 0.25 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
1
2
3
4
5
6
0
2
4
6
8
10
PHP2N20L
VGS, Gate-source voltage (Volts)
ID, Drain current (Amps)
VDS = 30 V
Tj = 175 C
Tj = 25 C
-60
-20
20
60
100
140
180
Tj / C
VGS(TO) / V
2
1
0
max.
typ.
min.
0
2
4
6
8
10
0
1
2
3
4
PHP2N20L
ID, Drain current (Amps)
gfs, Transconductance (S)
VDD = 30 V
Tj = 25 C
Tj = 175 C
0
0.4
0.8
1.2
1.6
2
2.4
VGS / V
ID / A
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
SUB-THRESHOLD CONDUCTION
2 %
typ
98 %
-60
-20
20
60
100
140
180
Tj / C
Normalised RDS(ON) = f(Tj)
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
a
1
10
100
1000
1
10
100
1000
PHP2N20L
VDS, Drain-source voltage (Volts)
Ciss, Coss, Crss, Junction capacitances (pF)
Crss
Coss
Ciss
September 1997
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHD3N20L
Logic level FET
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.14. Typical switching times.
t
d(on)
, t
r
, t
d(off)
, t
f
= f(R
G
)
Fig.15. Normalised drain-source breakdown voltage.
V
(BR)DSS
/V
(BR)DSS 25 C
= f(T
j
)
Fig.16. Source-Drain diode characteristic.
I
F
= f(V
SDS
); parameter T
j
Fig.17. Normalised unclamped inductive energy.
E
AS
% = f(T
j
)
Fig.18. Unclamped inductive test circuit.
0
5
10
15
0
2
4
6
8
10
PHP2N20L
Qg, Gate charge (nC)
VGS, Gate-Source voltage (Volts)
VDS = 40 V
100 V
160 V
ID = 3.3 A
Tj = 25 C
0
0.5
1
1.5
2
0
5
10
15
20
PHP2N20L
VSDS, Source-drain voltage (Volts)
IF, Source-drain diode current (Amps)
Tj = 25 C
Tj = 175 C
VGS = 0 V
0
20
40
60
80
100
1
10
100
1000
PHP2N20L
tr
td(off)
tf
td(on)
Tj = 25 C
VDD = 100 V
RD = 30 Ohms
VGS = 5 V
ID = 3.3 A
RG, Gate resistance (Ohms)
Switching times (ns)
20
40
60
80
100
120
140
160
180
120
110
100
90
80
70
60
50
40
30
20
10
0
Starting Tj ( C)
EAS, Normalised unclamped inductive energy (%)
-100
-50
0
50
100
150
0.85
0.9
0.95
1
1.05
1.1
1.15
Tj, Junction temperature (C)
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
E
AS
=
0.5
LI
D
2
V
(
BR
)
DSS
/(
V
(
BR
)
DSS
-
V
DD
)
September 1997
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHD3N20L
Logic level FET
MECHANICAL DATA
Dimensions in mm : Net Mass: 1.4 g
Fig.19. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.20. SOT428 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
6.22 max
2.38 max
0.93 max
6.73 max
0.3
10.4 max
0.5
0.8 max
(x2)
2.285 (x2)
0.5
seating plane
1.1
0.5 min
5.4
4 min
4.6
1
2
3
tab
7.0
7.0
2.15
2.5
4.57
1.5
September 1997
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
PHD3N20L
Logic level FET
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
September 1997
7
Rev 1.000
PDF 
ZIP