Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
FEATURES
SYMBOL
QUICK REFERENCE DATA
'Trench' technology
V
DSS
= 55 V
Very low on-state resistance
Fast switching
I
D
= 44 A
Stable off-state characteristics
High thermal cycling performance
R
DS(ON)
28 m
(V
GS
= 5 V)
Low thermal resistance
R
DS(ON)
26 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP44N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB44N06LT is supplied in the SOT404 surface mounting package.
The PHD44N06LT is supplied in the SOT428 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
SOT428
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 175C
-
55
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 175C; R
GS
= 20 k
-
55
V
V
GS
Gate-source voltage
-
13
V
I
D
Continuous drain current
T
mb
= 25 C
-
44
A
T
mb
= 100 C
-
31
A
I
DM
Pulsed drain current
T
mb
= 25 C
-
176
A
P
D
Total power dissipation
T
mb
= 25 C
-
114
W
T
j
, T
stg
Operating junction and
- 55
175
C
storage temperature
d
g
s
1
2
3
tab
1
3
tab
2
1 2 3
tab
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
September 1998
1
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-mb
Thermal resistance junction
-
1.31
K/W
to mounting base
R
th j-a
Thermal resistance junction
SOT78 package, in free air
60
-
K/W
to ambient
SOT404 and SOT428 packages, pcb
50
-
K/W
mounted, minimum footprint
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
C
Electrostatic discharge
Human body model (100 pF, 1.5 k
)
-
2
kV
capacitor voltage, all pins
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
55
-
-
V
voltage
T
j
= -55C
50
-
-
V
V
(BR)GSS
Gate-source breakdown
I
G
=
1 mA;
10
-
-
V
voltage
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1.0
1.5
2.0
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
-
2.3
V
R
DS(ON)
Drain-source on-state
V
GS
= 5 V; I
D
= 20 A
-
22
28
m
resistance
V
GS
= 10 V; I
D
= 20 A
-
20
26
m
T
j
= 175C
-
-
59
m
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
13
40
-
S
I
GSS
Gate source leakage current V
GS
=
5 V; V
DS
= 0 V
-
0.02
1
A
T
j
= 175C
-
-
20
A
I
DSS
Zero gate voltage drain
V
DS
= 55 V; V
GS
= 0 V;
-
0.05
10
A
current
T
j
= 175C
-
-
500
A
Q
g(tot)
Total gate charge
I
D
= 40 A; V
DD
= 44 V; V
GS
= 5 V
-
27.5
-
nC
Q
gs
Gate-source charge
-
7
-
nC
Q
gd
Gate-drain (Miller) charge
-
13
-
nC
t
d on
Turn-on delay time
V
DD
= 30 V; I
D
= 25 A;
-
22
32
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
G
= 10
-
85
125
ns
t
d off
Turn-off delay time
Resistive load
-
70
95
ns
t
f
Turn-off fall time
-
64
85
ns
L
d
Internal drain inductance
Measured from tab to centre of die
-
3.5
-
nH
L
d
Internal drain inductance
Measured from drain lead to centre of die
-
4.5
-
nH
(SOT78 package only)
L
s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
1300
1700
pF
C
oss
Output capacitance
-
250
300
pF
C
rss
Feedback capacitance
-
130
180
pF
September 1998
2
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
-
-
44
A
(body diode)
I
SM
Pulsed source current (body
-
-
176
A
diode)
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.95
1.2
V
I
F
= 40 A; V
GS
= 0 V
-
1.0
-
V
t
rr
Reverse recovery time
I
F
= 40 A; -dI
F
/dt = 100 A/
s;
-
41
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 30 V
-
0.16
-
C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 35 A; V
DD
25 V; V
GS
= 5 V;
-
70
mJ
unclamped inductive turn-off
R
GS
= 50
; T
mb
= 25 C
energy
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
September 1998
3
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
1
10
100
1
10
100
1000
ID/A
VDS/V
RDS(ON) = VDS/ID
tp =
1 us
10us
100 us
1 ms
10ms
100ms
DC
0
10
20
30
40
50
60
70
20
22
24
26
28
30
32
34
RDS(ON)/mOhm
VGS/V =
ID/A
4
4.2
4.4
4.6
4.8
5
1.0E-06
0.0001
0.01
1
100
0.01
0.1
1
10
Zth/ (K/W)
t/s
0.5
0.2
0.1
0.05
0.02
0
D =
t
p
t
p
T
T
P
t
D
0
1
2
3
4
5
6
0
10
20
30
40
50
60
70
80
ID/A
VGS/V
Tj/C =
175
25
0
2
4
6
8
10
0
20
40
60
80
100
10
8
6
4.8
VGS = 4.6 V
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
5
Drain current, ID (A)
Drain-source voltage, VDS (V)
0
10
20
30
40
50
60
70
80
5
10
15
20
25
30
35
40
Transconductance, gfs (S)
Drain current, ID (A)
September 1998
4
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 20 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 40 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
-100
-50
0
50
100
150
200
0.5
1
1.5
2
2.5
BUK959-60
Tmb / degC
Rds(on) normlised to 25degC
a
0.01
0.1
1
10
100
0
.5
1
1.5
2
2.5
3
Thousands pF
VDS/V
Ciss
Coss
Crss
BUK959-60
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
5
10
15
20
25
30
0
1
2
3
4
5
6
VGS/V
QG/nC
VDS = 14V
VDS = 44V
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
0
0.5
1
1.5
0
20
40
60
80
100
IF/A
VSDS/V
Tj/C =
175
25
September 1998
5
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 35 A
Fig.16. Avalanche energy test circuit.
20
40
60
80
100
120
140
160
180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
September 1998
6
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
10,3
max
3,7
2,8
3,0
3,0 max
not tinned
1,3
max
(2x)
1 2 3
2,4
0,6
4,5
max
5,9
min
15,8
max
1,3
2,54 2,54
0,9 max (3x)
13,5
min
September 1998
7
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
Fig.18. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.19. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
11 max
4.5 max
1.4 max
10.3 max
0.5
15.4
2.5
0.85 max
(x2)
2.54 (x2)
17.5
11.5
9.0
5.08
3.8
2.0
September 1998
8
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
MECHANICAL DATA
Dimensions in mm : Net Mass: 1.4 g
Fig.20. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.21. SOT428 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
6.22 max
2.38 max
0.93 max
6.73 max
0.3
10.4 max
0.5
0.8 max
(x2)
2.285 (x2)
0.5
seating plane
1.1
0.5 min
5.4
4 min
4.6
1
2
3
tab
7.0
7.0
2.15
2.5
4.57
1.5
September 1998
9
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP44N06LT, PHB44N06LT, PHD44N06LT
Logic level FET
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
September 1998
10
Rev 1.400
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