Document Outline
- FEATURES
- GENERAL DESCRIPTION
- SYMBOL
- PINNING
- QUICK REFERENCE DATA
- SOT96-1
- LIMITING VALUES
- THERMAL RESISTANCES
- ELECTRICAL CHARACTERISTICS
- REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
- MECHANICAL DATA
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
Philips Semiconductors
Product specification
P-channel enhancement mode
PHK04P02T
MOS transistor
FEATURES
SYMBOL
QUICK REFERENCE DATA
Very low threshold voltage
V
DS
= -16 V
Fast switching
Logic level compatible
I
D
= -4.66 A
Surface mount package
R
DS(ON)
0.15
(V
GS
= -2.5 V)
V
GS(TO)
0.4 V
GENERAL DESCRIPTION
PINNING
SOT96-1
P-channel, enhancement mode,
PIN
DESCRIPTION
logic
level,
field-effect
power
transistor. This device has low
1,2,3
source
threshold voltage and extremely
fast switching making it ideal for
4
gate
battery powered applications and
high speed digital interfacing.
5,6,7,8 drain
The PHK04P02T is supplied in the
SOT96-1 (SO8) surface mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
-16
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
-16
V
V
GS
Gate-source voltage
-
8
V
I
D
Drain current (DC)
T
sp
= 25 C
-
-4.66
A
T
sp
= 100 C
-
-1.87
A
I
DM
Drain current (pulse peak value)
T
sp
= 25 C
-
-26.4
A
P
tot
Total power dissipation
T
sp
= 25 C
-
5.0
W
T
sp
= 100 C
-
2.0
W
T
stg
, T
j
Storage & operating temperature
- 55
150
C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-sp
Thermal resistance junction to
mounted on metal clad substrate.
25
-
K/W
solder point
d
g
s
1
2
3
4
5
6
7
8
pin 1 index
May 2002
1
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
PHK04P02T
MOS transistor
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= -10
A
-16
-
-
V
voltage
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= -1 mA
-0.4
-0.6
-
V
T
j
= 150C
-0.1
-
-
V
R
DS(ON)
Drain-source on-state
V
GS
= -4.5 V; I
D
= -1 A
-
80
120
m
resistance
V
GS
= -2.5 V; I
D
= -1 A
-
117
150
m
V
GS
= -1.8 V; I
D
= -0.5 A
-
140
180
m
V
GS
= -2.5 V; I
D
= -1 A; T
j
= 150C
-
175
230
m
g
fs
Forward transconductance
V
DS
= -12.8 V; I
D
= -1 A
1.5
4.5
-
S
I
GSS
Gate source leakage current V
GS
=
8 V; V
DS
= 0 V
-
10
100
nA
I
DSS
Zero gate voltage drain
V
DS
= -12.8 V; V
GS
= 0 V;
-
-50
-100
nA
current
T
j
= 150C
-
-13
-100
A
Q
g(tot)
Total gate charge
I
D
= -1 A; V
DD
= -10 V; V
GS
= -4.5 V
-
7.2
-
nC
Q
gs
Gate-source charge
-
1.7
-
nC
Q
gd
Gate-drain (Miller) charge
-
1.83
-
nC
t
d on
Turn-on delay time
V
DD
= -10 V; I
D
= -1 A;
-
2
-
ns
t
r
Turn-on rise time
V
GS
= -8 V; R
G
= 6
-
4.5
-
ns
t
d off
Turn-off delay time
Resistive load
-
45
-
ns
t
f
Turn-off fall time
-
20
-
ns
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= -12.8 V; f = 1 MHz
-
528
-
pF
C
oss
Output capacitance
-
200
-
pF
C
rss
Feedback capacitance
-
57
-
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
DR
Continuous reverse drain
T
sp
= 25 C, t
5 s
-
-
-4.66
A
current
I
DRM
Pulsed reverse drain current
-
-
-26
A
V
SD
Diode forward voltage
I
F
= -0.62 A; V
GS
= 0 V
-
-0.62
-1.3
V
t
rr
Reverse recovery time
I
F
= -0.5 A; -dI
F
/dt = 100 A/
s;
-
75
-
ns
Q
rr
Reverse recovery charge
V
GS
= 0 V; V
R
= -12.8 V
-
69
-
nC
May 2002
2
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
PHK04P02T
MOS transistor
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
a
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
a
); conditions: V
GS
-10 V
Fig.3. Safe operating area. T
sp
= 25 C;
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
.
Fig.4. Transient thermal impedance. Z
th j-sp
= f(t);
parameter D = t
p
/T;;
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
Normalised Power Derating, Ptot (%)
0
10
20
30
40
50
60
70
80
90
100
0
20
40
60
80
100
120
140
160
Ambient temperature, Ta (C)
0.01
1
10
100
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Zth j-sp (K/W)
0.001
0.1
single pulse
D = 0.5
D = 0.2
D = 0.1
D = 0.05
D = 0.02
1E-02
1E-01
tp
D = tp/T
D
P
T
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
-2
-1.5
-1
-0.5
0
Drain-Source Voltage, VDS (V)
Drain current, ID (A)
VGS = -0.8 V
-0.9 V
-4.5 V
-1.2 V
-1 V
Tj = 25 C
-1.1 V
-1.3 V
-1.8 V
-2.5 V
Normalised Current Derating, ID (%)
0
20
40
60
80
100
120
0
20
40
60
80
100
120
140
160
Ambient temperature, Ta (C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS = -4.5V
-1.2 V
-1V
Tj = 25 C
-0.8 V
-1.1 V
-0.9 V
-2.5 V
-1.3 V
-1.8 V
0.01
0.1
1
10
100
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
DC
100 ms
10 ms
RDS(on) = VDS/ ID
tp = 1ms
May 2002
3
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
PHK04P02T
MOS transistor
Fig.7. Typical transfer characteristics; I
D
= f(V
GS
)
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
-5
-4
-3
-2
-1
0
-2
-1.5
-1
-0.5
0
Gate-Source Voltage, VGS (V)
VDS > ID X RDS(on)
Tj = 25 C
150 C
Drain Current, ID (A)
Threshold Voltage, VGS(to), (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
25
50
75
100
125
150
Junction Temperature, Tj (C)
minimum
typical
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
-1
-0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0
Gate-Source Voltage, VGS (V)
Drain Current, ID (A)
VDS = -5 V
Tj = 25 C
0
1
2
3
4
5
6
7
8
-2.6
-2.4
-2.2
-2
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
Drain Current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
150 C
VDS > ID X RDS(on)
10
100
1000
-0.1
-1.0
-10.0
-100.0
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
Normalised Drain-Source On Resistance
0.6
0.8
1.0
1.2
1.4
1.6
0
25
50
75
100
125
150
Junction Temperature, Tj (C)
-2.5 V
-1.8 V
VGS = -4.5 V
RDS(on) @ Tj
RDS(on) @ 25 oC
May 2002
4
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
PHK04P02T
MOS transistor
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
-5
-4
-3
-2
-1
0
0
1
2
3
4
5
6
7
8
9
Gate charge, (nC)
Gate-source voltage, VGS (V)
VDD = 10 V
RD = 10 Ohms
s
Tj = 25 C
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
150 C
May 2002
5
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
PHK04P02T
MOS transistor
MECHANICAL DATA
Fig.15. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(2)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
0.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.4
SOT96-1
X
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
4
5
pin 1 index
1
8
y
076E03S
MS-012AA
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.20
0.19
0.16
0.15
0.050
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.01
0.041
0.004
0.039
0.016
0
2.5
5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
95-02-04
97-05-22
May 2002
6
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
PHK04P02T
MOS transistor
DEFINITIONS
DATA SHEET STATUS
DATA SHEET
PRODUCT
DEFINITIONS
STATUS
1
STATUS
2
Objective data
Development
This data sheet contains data from the objective specification for
product development. Philips Semiconductors reserves the right to
change the specification in any manner without notice
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in
order to improve the design, manufacturing and supply. Changes will
be communicated according to the Customer Product/Process
Change Notification (CPCN) procedure SNW-SQ-650A
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design.
2 The product status of the device(s) described in this datasheet may have changed since this datasheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
May 2002
7
Rev 1.000
PDF 
ZIP