Document Outline
- FEATURES
- SYMBOL
- QUICK REFERENCE DATA
- GENERAL DESCRIPTION
- PINNING
- SOT96-1 (SO8)
- LIMITING VALUES
- THERMAL RESISTANCES
- ELECTRICAL CHARACTERISTICS
- REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
- MECHANICAL DATA
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHK5NQ10T
FEATURES
SYMBOL
QUICK REFERENCE DATA
Low on-state resistance
Fast switching
V
DS
= 100 V
Low profile surface mount
package
I
D
= 5 A
R
DS(ON)
50 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
PINNING
SOT96-1 (SO8)
N-channel
enhancement
mode
PIN
DESCRIPTION
field-effect transistor in a plastic
envelope
using
'trench'
1-3
source
technology.
4
gate
Applications:-
Motor and relay drivers
5-8
drain
d.c. to d.c. converters
The PHK5NQ10T is supplied in the
SOT96-1 (SO8) surface mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 150C
-
100
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 150C;
-
100
V
R
GS
= 20 k
V
GS
Gate-source voltage
-
20
V
I
D
Drain current (t
p
10 s)
T
a
= 25 C
-
5
A
T
a
= 70 C
-
3.6
A
I
DM
Drain current (pulse peak value)
T
a
= 25 C
-
20
A
P
tot
Total power dissipation
T
a
= 25 C, t
10 s
-
2.5
W
T
a
= 70 C, t
10 s
-
1.6
W
T
j
, T
stg
Operating junction and storage
- 65
150
C
temperature
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-a
Thermal resistance junction
Surface mounted, FR4 board, t
10 sec
-
50
K/W
to ambient
R
th j-a
Thermal resistance junction
Surface mounted, FR4 board
150
-
K/W
to ambient
d
g
s
1
2
3
4
5
6
7
8
pin 1 index
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHK5NQ10T
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 10
A;
100
-
-
V
voltage
T
j
= -55C
89
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
2
3
4
V
T
j
= 150C
1.1
-
-
V
T
j
= -55C
-
6
V
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 5 A
-
40
50
m
resistance
T
j
= 150C
-
-
120
m
I
GSS
Gate source leakage current V
GS
=
20 V; V
DS
= 0 V
-
10
100
nA
I
DSS
Zero gate voltage drain
V
DS
= 100 V; V
GS
= 0 V
-
0.05
10
A
current
T
j
= 150C
-
-
100
A
Q
g(tot)
Total gate charge
I
D
= 5 A; V
DD
= 80 V; V
GS
= 10 V
-
30
-
nC
Q
gs
Gate-source charge
-
4
-
nC
Q
gd
Gate-drain (Miller) charge
-
11
-
nC
t
d on
Turn-on delay time
V
DD
= 50 V; R
D
= 10
;
-
8
-
ns
t
r
Turn-on rise time
V
GS
= 10 V; R
G
= 5.6
-
14
-
ns
t
d off
Turn-off delay time
Resistive load
-
35
-
ns
t
f
Turn-off fall time
-
15
-
ns
L
d
Internal drain inductance
Measured from drain lead to centre of die
-
1
-
nH
L
s
Internal source inductance
Measured from source lead to source
-
3
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 20 V; f = 1 MHz
-
1240
-
pF
C
oss
Output capacitance
-
172
-
pF
C
rss
Feedback capacitance
-
100
-
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
T
a
= 25 C, t
p
10 s
-
-
2.3
A
(body diode)
I
SM
Pulsed source current (body
-
-
18
A
diode)
V
SD
Diode forward voltage
I
F
= 5 A; V
GS
= 0 V
-
0.82
1.2
V
t
rr
Reverse recovery time
I
F
= 5 A; -dI
F
/dt = 100 A/
s;
-
65
-
ns
Q
rr
Reverse recovery charge
V
GS
= 0 V; V
R
= 25 V
-
100
-
nC
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHK5NQ10T
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
a
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
a
); V
GS
10 V
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-a
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
)
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
)
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
Ambient temperature, Ta (C)
0.01
0.1
1
10
100
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Transient thermal impedance, Zth j-a (K/W)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
Ambient temperature, Ta (C)
0
2
4
6
8
10
12
14
16
18
20
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
4.6 V
Tj = 25 C
VGS = 10V
4.8 V
8 V
4.4 V
5 V
6 V
4.2 V
4 V
0.01
0.1
1
10
100
0.1
1
10
100
1000
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
0
2
4
6
8
10
12
14
16
18
20
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS = 10V
Tj = 25 C
6V
8 V
4.4
4.8
5 V
4.6
4.2
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHK5NQ10T
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
150 C
Threshold Voltage, VGS(TO) (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
typical
maximum
minimum
0
5
10
15
20
25
0
1
2
3
4
5
6
7
8
9
10
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
150 C
VDS > ID X RDS(ON)
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Gate-source voltage, VGS (V)
minimum
typical
maximum
Normalised On-state Resistance
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Junction temperature, Tj (C)
10
100
1000
10000
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHK5NQ10T
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
5
10
15
20
25
30
35
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 5A
Tj = 25 C
VDD = 20 V
VDD = 80 V
0
1
2
3
4
5
6
7
8
9
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
150 C
VGS = 0 V
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHK5NQ10T
MECHANICAL DATA
Fig.15. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(2)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
0.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.4
SOT96-1
X
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
4
5
pin 1 index
1
8
y
076E03S
MS-012AA
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.20
0.19
0.16
0.15
0.050
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.01
0.041
0.004
0.039
0.016
0
2.5
5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
95-02-04
97-05-22
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHK5NQ10T
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
7
Rev 1.000
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