Philips Semiconductors
Product specification
Dual N-channel enhancement mode
PHN210
TrenchMOS
TM
transistor
FEATURES
SYMBOL
QUICK REFERENCE DATA
Dual device
V
DS
= 30 V
Low threshold voltage
Fast switching
I
D
= 3.4 A
Logic level compatible
Surface mount package
R
DS(ON)
100 m
(V
GS
= 10 V)
R
DS(ON)
200 m
(V
GS
= 4.5 V)
GENERAL DESCRIPTION
PINNING
SOT96-1
Dual
N-channel
enhancement
PIN
DESCRIPTION
mode field-effect transistor in a
plastic envelope using 'trench'
1
source 1
technology.
2
gate 1
Applications:-
Motor and relay drivers
3
source 2
d.c. to d.c. converters
Logic level translator
4
gate 2
The PHN210 is supplied in the
5,6
drain 2
SOT96-1 (SO8) surface mounting
package.
7,8
drain 1
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Repetitive peak drain-source
T
j
= 25 C to 150C
-
30
V
voltage
V
DS
Continuous drain-source voltage
-
30
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
-
30
V
V
GS
Gate-source voltage
-
20
V
I
D
Drain current per MOSFET
1
T
a
= 25 C
-
3.4
A
T
a
= 70 C
-
2.8
A
I
D
Drain current per MOSFET (both
T
a
= 25 C
-
2.4
A
MOSFETs conducting)
1
T
a
= 70 C
-
1.9
A
I
DM
Drain current per MOSFET (pulse
T
a
= 25 C
-
14
A
peak value)
P
tot
Total power dissipation (either or
T
a
= 25 C
-
2
W
both MOSFETs conducting)
1
T
a
= 70 C
-
1.3
W
T
stg
, T
j
Storage & operating temperature
- 65
150
C
d1
g1
s1
d1
d2
g2
d2
s2
1
2
3
4
5
6
7
8
pin 1 index
1 Surface mounted on FR4 board, t
10 sec
February 1999
1
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
PHN210
TrenchMOS
TM
transistor
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-a
Thermal resistance junction
Surface mounted, FR4 board, t
10 sec
-
62.5
K/W
to ambient
R
th j-a
Thermal resistance junction
Surface mounted, FR4 board
150
-
K/W
to ambient
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
E
AS
Non-repetitive avalanche
Unclamped inductive load, I
AS
= 3.4 A;
-
13
mJ
energy (per MOSFET)
t
p
= 0.2 ms; T
j
prior to avalanche = 25C;
V
DD
15 V; R
GS
= 50
; V
GS
= 10 V
I
AS
Non-repetitive avalanche
-
3.4
A
current (per MOSFET)
ELECTRICAL CHARACTERISTICS
T
j
= 25C, per MOSFET unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 10
A;
30
-
-
V
voltage
T
j
= -55C
27
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1
2
2.8
V
T
j
= 150C
0.4
-
-
V
T
j
= -55C
-
3.2
V
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 2.2 A
-
80
100
m
resistance
V
GS
= 4.5 V; I
D
= 1 A
-
120
200
m
V
GS
= 10 V; I
D
= 2.2 A; T
j
= 150C
-
-
170
m
g
fs
Forward transconductance
V
DS
= 20 V; I
D
= 2.2 A
2
4.5
-
S
I
D(ON)
On-state drain current
V
GS
= 10 V; V
DS
= 1 V;
3.5
-
-
A
V
GS
= 4.5 V; V
DS
= 5 V
2
-
-
A
I
DSS
Zero gate voltage drain
V
DS
= 24 V; V
GS
= 0 V;
-
10
100
nA
current
V
DS
= 24 V; V
GS
= 0 V; T
j
= 150C
-
0.6
10
A
I
GSS
Gate source leakage current V
GS
=
20 V; V
DS
= 0 V
-
10
100
nA
Q
g(tot)
Total gate charge
I
D
= 2.3 A; V
DD
= 15 V; V
GS
= 10 V
-
6
-
nC
Q
gs
Gate-source charge
-
0.7
-
nC
Q
gd
Gate-drain (Miller) charge
-
0.7
-
nC
t
d on
Turn-on delay time
V
DD
= 20 V; R
D
= 18
;
-
6
-
ns
t
r
Turn-on rise time
V
GS
= 10 V; R
G
= 6
-
8
-
ns
t
d off
Turn-off delay time
Resistive load
-
21
-
ns
t
f
Turn-off fall time
-
15
-
ns
L
d
Internal drain inductance
Measured from drain lead to centre of die
-
2.5
-
nH
L
s
Internal source inductance
Measured from source lead to source
-
5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 20 V; f = 1 MHz
-
250
-
pF
C
oss
Output capacitance
-
88
-
pF
C
rss
Feedback capacitance
-
54
-
pF
February 1999
2
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
PHN210
TrenchMOS
TM
transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C, per MOSFET unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source diode
T
a
= 25 C
-
-
2.2
A
current (per MOSFET)
I
SM
Pulsed source diode current
-
-
14
A
(per MOSFET)
V
SD
Diode forward voltage
I
F
= 1.25 A; V
GS
= 0 V
-
0.82
1.2
V
t
rr
Reverse recovery time
I
F
= 1.25 A; -dI
F
/dt = 100 A/
s;
-
69
-
ns
Q
rr
Reverse recovery charge
V
GS
= 0 V; V
R
= 25 V
-
55
-
nC
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
a
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
a
); conditions: V
GS
10 V
Fig.3. Safe operating area. T
a
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-a
= f(t); parameter D = t
p
/T
0
20
40
60
80
100
120
140
Tamb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
PHN210
0.01
0.1
1
10
100
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
10 s
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
0
20
40
60
80
100
120
140
Ambient temperature, Tamb (C)
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
PHN210
0.01
0.1
1
10
100
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Peak Pulsed Drain Current, IDM (A)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
February 1999
3
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
PHN210
TrenchMOS
TM
transistor
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
) ; parameter T
j
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
0
1
2
3
4
5
6
7
8
9
10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
3.2 V
3.4 V
4 V
Tj = 25 C
VGS = 20 V
3.6 V
3.8 V
5V
10 V
4.2 V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
150 C
0
0.1
0.2
0.3
0.4
0.5
0
1
2
3
4
5
6
7
8
9
10
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS =5 V
4.2 V
20V
Tj = 25 C
3.8V
4 V
3.6 V
10V
3.2 V
3.4 V
-50
0
50
100
150
0
0.5
1
1.5
2
SOT223 30V Trench
Tj / C
a
Normalised RDS(ON) = f(Tj)
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
150 C
-60
-40
-20
0
20
40
60
80
100 120 140
Tj / C
VGS(TO) / V
4
3
2
1
0
max.
typ.
min.
February 1999
4
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
PHN210
TrenchMOS
TM
transistor
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
p
);
unclamped inductive load
0
1
2
3
4
5
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
typ
min
max
0
1
2
3
4
5
6
7
8
9
10
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
Drain-Source Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
150 C
VGS = 0 V
10
100
1000
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
PHN210
0.1
1
10
1E-06
1E-05
1E-04
1E-03
1E-02
Avalanche time, tp (s)
Non-repetitive Avalanche current, IAS (A)
25 C
VDS
ID
tp
Tj prior to avalanche =125 C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 2.3A
Tj = 25 C
VDD = 15 V
February 1999
5
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
PHN210
TrenchMOS
TM
transistor
MECHANICAL DATA
Fig.16. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(2)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
0.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.4
SOT96-1
X
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
4
5
pin 1 index
1
8
y
076E03S
MS-012AA
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.20
0.19
0.16
0.15
0.050
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.01
0.041
0.004
0.039
0.016
0
2.5
5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
95-02-04
97-05-22
February 1999
6
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
PHN210
TrenchMOS
TM
transistor
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
February 1999
7
Rev 1.000
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