Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP24N03LT, PHB24N03LT
Logic level FET
FEATURES
SYMBOL
QUICK REFERENCE DATA
'Trench' technology
V
DSS
= 30 V
Very low on-state resistance
Fast switching
I
D
= 24 A
Stable off-state characteristics
High thermal cycling performance
R
DS(ON)
56 m
(V
GS
= 5 V)
Low thermal resistance
R
DS(ON)
50 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP24N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB24N03LT is supplied in the SOT404 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 175C
-
30
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 175C; R
GS
= 20 k
-
30
V
V
GS
Gate-source voltage
-
13
V
I
D
Continuous drain current
T
mb
= 25 C; V
GS
= 5 V
-
24
A
T
mb
= 100 C; V
GS
= 5 V
-
20
A
I
DM
Pulsed drain current
T
mb
= 25 C
-
96
A
P
D
Total power dissipation
T
mb
= 25 C
-
60
W
T
j
, T
stg
Operating junction and
- 55
175
C
storage temperature
d
g
s
1
3
tab
2
1 2 3
tab
1 It is not possible to make connection to pin 2 of the SOT404 package.
January 1998
1
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP24N03LT, PHB24N03LT
Logic level FET
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
C
Electrostatic discharge
Human body model (100 pF, 1.5 k
)
-
2
kV
capacitor voltage, all pins
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction
-
-
2.5
K/W
to mounting base
R
th j-a
Thermal resistance junction
SOT78 package, in free air
-
60
-
K/W
to ambient
SOT404 package, pcb mounted, minimum
-
50
-
K/W
footprint
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
30
-
-
V
voltage
T
j
= -55C
27
-
-
V
V
(BR)GSS
Gate-source breakdown
I
G
= 1 mA
10
-
-
V
voltage
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1
1.5
2
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
-
2.3
V
R
DS(ON)
Drain-source on-state
V
GS
= 5 V; I
D
= 25 A
-
50
56
m
resistance
V
GS
= 10 V; I
D
= 25 A
-
45
50
m
V
GS
= 5 V; I
D
= 12 A; T
j
= 175C
-
-
104
m
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 12 A
3
5
-
S
I
GSS
Gate-source leakage current V
GS
=
5 V; V
DS
= 0 V;
-
0.02
1
A
T
j
= 175C
-
-
10
A
I
DSS
Zero gate voltage drain
V
DS
= 30 V; V
GS
= 0 V;
-
0.05
10
A
current
T
j
= 175C
-
-
500
A
Q
g(tot)
Total gate charge
I
D
= 10 A; V
DD
= 30 V; V
GS
= 5 V
-
9
-
nC
Q
gs
Gate-source charge
-
2.3
-
nC
Q
gd
Gate-drain (Miller) charge
-
5.4
-
nC
t
d on
Turn-on delay time
V
DD
= 30 V; I
D
= 25 A;
-
12
-
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
G
= 10
-
50
-
ns
t
d off
Turn-off delay time
Resistive load
-
30
-
ns
t
f
Turn-off fall time
-
36
-
ns
L
d
Internal drain inductance
Measured tab to centre of die
-
3.5
-
nH
L
d
Internal drain inductance
Measured from drain lead to centre of die
-
4.5
-
nH
(SOT78 package only)
L
s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
460
-
pF
C
oss
Output capacitance
-
144
-
pF
C
rss
Feedback capacitance
-
78
-
pF
January 1998
2
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP24N03LT, PHB24N03LT
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
-
-
24
A
(body diode)
I
SM
Pulsed source current (body
-
-
96
A
diode)
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
1.05
1.5
V
t
rr
Reverse recovery time
I
F
= 12 A; -dI
F
/dt = 100 A/
s;
-
50
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 25 V
-
0.1
-
C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 12 A; V
DD
15 V;
-
15
mJ
unclamped inductive turn-off
V
GS
= 5 V; R
GS
= 50
; T
mb
= 25 C
energy
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
January 1998
3
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP24N03LT, PHB24N03LT
Logic level FET
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
)
1
10
100
1
10
100
PHP24N03T
VDS, Drain-source voltage (Volts)
ID, Drain current (Amps)
100 us
1 ms
10 ms
DC
10 us
RDS(ON) = VDS/ID
Tmb = 25 C
0
5
10
15
20
0
0.02
0.04
0.06
0.08
0.1
0.12
PHP24N03LT
ID, Drain current (Amps)
RDS(on), Drain-Source on resistance (Ohms)
VGS = 2.5 V
3 V
3.5 V
5 V
15 V
Tj = 25 C
1us
10us 100us
1ms
10ms
0.1s
1s
10s
0.01
0.1
1
10
0
0.2
0.1
0.05
0.02
0.5
PHP24N03T
pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
D =
t
p
t
p
T
T
P
t
D
D =
0
1
2
3
4
5
0
5
10
15
20
PHP24N03LT
Gate-source voltage, VGS (V)
Drain current, ID (A)
Tj = 25 C
175 C
VDS = 25 V
0
5
10
15
20
25
30
0
5
10
15
20
VGS = 2.5 V
3 V
3.5 V
PHP24N03LT
VDS, Drain-Source voltage (Volts)
ID, Drain current (Amps)
5 V
15 V
Tj = 25 C
0
5
10
15
20
0
5
10
15
PHP24N03LT
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
VDS = 25 V
175 C
January 1998
4
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP24N03LT, PHB24N03LT
Logic level FET
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 12 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); parameter T
j
-100
0
100
200
0
0.5
1
1.5
2
30V TrenchMOS
Tj / C
a
150
50
-50
1
10
100
1000
10
100
1000
PHP24N03LT
Drain-source voltage, VDS (V)
Capacitances Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
Tj = 25 C
BUK959-60
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
0
5
10
15
20
25
0
5
10
15
PHP24N03LT
Qg, Gate charge (nC)
VGS, Gate-Source voltage (Volts)
VDD = 30 V
ID = 10 A
Tj = 25 C
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
5
10
15
20
PHP24N03LT
Source-Drain voltage, VSDS (V)
Source-Drain diode current, IF(A)
Tj = 25 C
VGS = 0 V
175 C
January 1998
5
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP24N03LT, PHB24N03LT
Logic level FET
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
)
Fig.16. Avalanche energy test circuit.
20
40
60
80
100
120
140
160
180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
=
0.5
LI
D
2
BV
DSS
/(
BV
DSS
-
V
DD
)
January 1998
6
Rev 1.300
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