Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP42N03LT, PHB42N03LT
Logic level FET
FEATURES
SYMBOL
QUICK REFERENCE DATA
'Trench' technology
V
DSS
= 30 V
Very low on-state resistance
Fast switching
I
D
= 42 A
Stable off-state characteristics
High thermal cycling performance
R
DS(ON)
26 m
(V
GS
= 5 V)
Low thermal resistance
R
DS(ON)
23 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP42N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB42N03LT is supplied in the SOT404 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 175C
-
30
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 175C; R
GS
= 20 k
-
30
V
V
GS
Gate-source voltage
-
15
V
I
D
Continuous drain current
T
mb
= 25 C; V
GS
= 5 V
-
42
A
T
mb
= 100 C; V
GS
= 5 V
-
30
A
I
DM
Pulsed drain current
T
mb
= 25 C
-
168
A
P
D
Total power dissipation
T
mb
= 25 C
-
86
W
T
j
, T
stg
Operating junction and
- 55
175
C
storage temperature
d
g
s
1
3
tab
2
1 2 3
tab
November 1998
1
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP42N03LT, PHB42N03LT
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction
-
-
1.75
K/W
to mounting base
R
th j-a
Thermal resistance junction
SOT78 package, in free air
-
60
-
K/W
to ambient
SOT404 package, pcb mounted, minimum
-
50
-
K/W
footprint
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
30
-
-
V
voltage
T
j
= -55C
27
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1
1.5
2
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
-
2.3
V
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 25 A
-
16
23
m
resistance
V
GS
= 5 V; I
D
= 25 A
-
20
26
m
V
GS
= 5 V; I
D
= 25 A; T
j
= 175C
-
-
48
m
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
8
27
-
S
I
DSS
Zero gate voltage drain
V
DS
= 30 V; V
GS
= 0 V;
-
0.05
10
A
current
T
j
= 175C
-
-
500
A
I
GSS
Gate source leakage current V
GS
=
5 V; V
DS
= 0 V
-
10
100
nA
Q
g(tot)
Total gate charge
I
D
= 20 A; V
DD
= 24 V; V
GS
= 10 V
-
40
-
nC
Q
gs
Gate-source charge
-
7
-
nC
Q
gd
Gate-drain (Miller) charge
-
10
-
nC
t
d on
Turn-on delay time
V
DD
= 15 V; I
D
= 25 A;
-
12
20
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
G
= 5
-
80
130
ns
t
d off
Turn-off delay time
Resistive load
-
35
60
ns
t
f
Turn-off fall time
-
31
45
ns
L
d
Internal drain inductance
Measured tab to centre of die
-
3.5
-
nH
L
d
Internal drain inductance
Measured from drain lead to centre of die
-
4.5
-
nH
(SOT78 package only)
L
s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
1050
-
pF
C
oss
Output capacitance
-
270
-
pF
C
rss
Feedback capacitance
-
140
-
pF
November 1998
2
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP42N03LT, PHB42N03LT
Logic level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
-
-
45
A
(body diode)
I
SM
Pulsed source current (body
-
-
180
A
diode)
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.95
1.2
V
I
F
= 40 A; V
GS
= 0 V
-
1.0
-
t
rr
Reverse recovery time
I
F
= 40 A; -dI
F
/dt = 100 A/
s;
-
52
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 25 V
-
0.08
-
C
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
0
20
40
60
80
100
120
140
160
180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1
10
100
1
10
100
1000
PHP42N03LT
VDS, Drain-source voltage (Volts)
ID, Drain current (Amps)
RDS(ON) = VDS/ID
1 ms
100 ms
tp = 10us
DC
10 ms
100 us
Tmb = 25 C
0
20
40
60
80
100
120
140
160
180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1E-07
1E-05
1E-03
1E-01
1E+01
0.01
0.1
1
10
7528-30
t / s
Zth j-mb / (K/W)
D =
t
p
t
p
T
T
P
t
D
D =
0
0.02
0.05
0.1
0.2
0.5
November 1998
3
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP42N03LT, PHB42N03LT
Logic level FET
Fig.5. Typical output characteristics
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Fig.8. Typical transconductance
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
0
2
4
6
8
10
0
10
20
30
40
50
60
70
80
PHP45N03LT
VDS, Drain-Source voltage (Volts)
ID, Drain current (Amps)
VGS = 2.5 V
3 V
3.5 V
4 V
4.5 V
5 V
10 V
15 V
Tj = 25 C
0
10
20
30
40
50
0
5
10
15
20
25
30
PHP45N03LT
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
175 C
VDS = 25 V
0
10
20
30
40
50
60
70
80
0
0.01
0.02
0.03
0.04
0.05
0.06
PHP45N03LT
ID, Drain current (Amps)
Drain-Source on resistance, RDS(on) (Ohms)
VGS = 15 V
10 V
3 V
3.5 V
4 V
4.5 V
5 V
Tj = 25 C
-100
0
100
200
0
0.5
1
1.5
2
30V TrenchMOS
Tj / C
a
150
50
-50
0
1
2
3
4
5
6
0
10
20
30
40
50
PHP45N03LT
Gate-source voltage, VGS (V)
Drain current, ID (A)
Tj = 25 C
175 C
VDS = 25 V
BUK959-60
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
November 1998
4
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOS
TM
transistor
PHP42N03LT, PHB42N03LT
Logic level FET
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
)
0
0.5
1
1.5
2
2.5
3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01
Sub-Threshold Conduction
2%
typ
98%
0
10
20
30
40
50
0
5
10
15
PHP50N03LT
Qg, Gate charge (nC)
VGS, Gate-Source voltage (Volts)
VDD=24V
ID=20A
Tj = 25C
0.1
1
10
100
100
1000
10000
9528-30
VDS / V
C / pF
Ciss
Coss
Crss
0
0.5
1
1.5
2
0
10
20
30
40
50
60
9528-30
VSDS / V
IF / A
Tj / C = 175
25
November 1998
5
Rev 1.400
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