PHP/PHB/PHD45N03LTA
N-channel enhancement mode field-effect transistor
Rev. 02 -- 02 November 2001
Product data
1.
Description
N-channel logic level field-effect power transistor in a plastic package using
TrenchMOSTM
1
technology.
Product availability:
PHP45N03LTA in SOT78 (TO-220AB)
PHB45N03LTA in SOT404 (D
2
-PAK)
PHD45N03LTA in SOT428 (D-PAK).
2.
Features
s
Low on-state resistance
s
Fast switching.
3.
Applications
s
Computer motherboard high frequency DC to DC converters.
4.
Pinning information
[1]
It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.
1.
TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.
Table 1:
Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Pin
Description
Simplified outline
Symbol
1
gate (g)
SOT78 (TO-220AB)
SOT404 (D
2
-PAK)
SOT428 (D-PAK)
2
drain (d)
[1]
3
source (s)
mb
mounting base,
connected to drain (d)
MBK106
1 2
mb
3
1
3
2
MBK116
mb
MBK091
Top view
1
3
mb
2
s
d
g
MBB076
Philips Semiconductors
PHP/PHB/PHD45N03LTA
N-channel enhancement mode field-effect transistor
Product data
Rev. 02 -- 02 November 2001
2 of 14
9397 750 09023
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
5.
Quick reference data
6.
Limiting values
Table 2:
Quick reference data
Symbol Parameter
Conditions
Typ
Max
Unit
V
DS
drain-source voltage (DC)
T
j
= 25 to 175
C
-
25
V
I
D
drain current (DC)
T
mb
= 25
C; V
GS
= 5 V
-
40
A
P
tot
total power dissipation
T
mb
= 25
C
-
65
W
T
j
junction temperature
-
175
C
R
DSon
drain-source on-state resistance
V
GS
= 10 V; I
D
= 25 A
13
21
m
V
GS
= 5 V; I
D
= 25 A
17.5
24
m
V
GS
= 3.5 V; I
D
= 5.2 A
22
40
m
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
V
DS
drain-source voltage (DC)
T
j
= 25 to 175
C
-
25
V
V
DGR
drain-gate voltage (DC)
T
j
= 25 to 175
C; R
GS
= 20 k
-
25
V
V
GS
gate-source voltage (DC)
-
15
V
V
GSM
gate-source voltage
t
p
50
s; pulsed;
duty cycle 25 %; T
j
150
C
-
20
V
I
D
drain current (DC)
T
mb
= 25
C; V
GS
= 5 V;
Figure 2
and
3
-
40
A
T
mb
= 100
C; V
GS
= 5 V;
Figure 2
-
30
A
I
DM
peak drain current
T
mb
= 25
C; pulsed; t
p
10
s;
Figure 3
-
160
A
P
tot
total power dissipation
T
mb
= 25
C;
Figure 1
-
65
W
T
stg
storage temperature
-
55
+175
C
T
j
operating junction temperature
-
55
+175
C
Source-drain diode
I
S
source (diode forward) current (DC)
T
mb
= 25
C
-
40
A
I
SM
peak source (diode forward) current T
mb
= 25
C; pulsed; t
p
10
s
-
160
A
Avalanche ruggedness
E
AS
non-repetitive avalanche energy
unclamped inductive load;
I
D
= 40 A; t
p
= 0.1 ms; V
DD
= 15 V;
R
GS
= 50
; V
GS
= 5V; starting T
j
= 25
C;
-
60
mJ
Philips Semiconductors
PHP/PHB/PHD45N03LTA
N-channel enhancement mode field-effect transistor
Product data
Rev. 02 -- 02 November 2001
3 of 14
9397 750 09023
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Fig 1.
Normalized total power dissipation as a
function of mounting base temperature.
Fig 2.
Normalized continuous drain current as a
function of mounting base temperature.
T
mb
= 25
C; I
DM
is single pulse.
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
03aa16
0
40
80
120
0
50
100
150
200
Tmb (
o
C)
Pder
(%)
03aa24
0
40
80
120
0
50
100
150
200
Tmb
(
o
C)
I der
(%)
P
der
P
tot
P
tot 25 C
(
)
----------------------
100%
=
I
der
I
D
I
D 25 C
(
)
-------------------
100%
=
03af58
1
10
102
103
1
10
102
VDS (V)
ID
(A)
D.C.
10 ms
RDSon = VDS
/ ID
1 ms
tp = 10 s
100 s
tp
tp
T
P
t
T
=
Philips Semiconductors
PHP/PHB/PHD45N03LTA
N-channel enhancement mode field-effect transistor
Product data
Rev. 02 -- 02 November 2001
4 of 14
9397 750 09023
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
7.
Thermal characteristics
7.1 Transient thermal impedance
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Value
Unit
R
th(j-mb)
thermal resistance from junction to mounting
base
Figure 4
2.3
K/W
R
th(j-a)
thermal resistance from junction to ambient
vertical in still air; SOT78 package
60
K/W
mounted on a printed circuit board; minimum
footprint; SOT404 and SOT428 packages
50
K/W
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration.
03af57
10-2
10-1
1
10
10-5
10-4
10-3
10-2
10-1
1
t
p
(s)
Z
th(j-mb)
(K/W)
single pulse
= 0.5
0.2
0.1
0.05
0.02
tp
tp
T
P
t
T
=
Philips Semiconductors
PHP/PHB/PHD45N03LTA
N-channel enhancement mode field-effect transistor
Product data
Rev. 02 -- 02 November 2001
5 of 14
9397 750 09023
Koninklijke Philips Electronics N.V. 2001. All rights reserved.
8.
Characteristics
Table 5:
Characteristics
T
j
= 25
C unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 0.25 mA; V
GS
= 0 V
T
j
= 25
C
25
-
-
V
T
j
=
-
55
C
22
-
-
V
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
C
1
1.5
2
V
T
j
= 175
C
0.5
-
-
V
T
j
=
-
55
C
-
-
2.3
V
I
DSS
drain-source leakage current
V
DS
= 25 V; V
GS
= 0 V
T
j
= 25
C
-
0.05
10
A
T
j
= 175
C
-
-
500
A
I
GSS
gate-source leakage current
V
GS
=
5 V; V
DS
= 0 V
-
10
100
nA
R
DSon
drain-source on-state resistance
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
C
-
17.5
24
m
T
j
= 175
C
-
30
40.8
m
V
GS
= 10 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
C
-
13
21
m
V
GS
= 3.5 V; I
D
= 5.2 A;
Figure 7
and
8
T
j
= 25
C
-
22
40
m
Dynamic characteristics
Q
g(tot)
total gate charge
I
D
= 40 A; V
DD
= 24 V; V
GS
= 5 V;
Figure 13
-
19
-
nC
Q
gs
gate-source charge
-
5
-
nC
Q
gd
gate-drain (Miller) charge
-
8
11
nC
C
iss
input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 11
-
700
-
pF
C
oss
output capacitance
-
290
-
pF
C
rss
reverse transfer capacitance
-
200
-
pF
t
d(on)
turn-on delay time
V
DD
= 15 V; I
D
= 15 A; V
GS
= 10 V;
R
G
= 6
; resistive load
-
10
20
ns
t
r
turn-on rise time
-
60
90
ns
t
d(off)
turn-off delay time
-
35
60
ns
t
f
turn-off fall time
-
40
60
ns
Source-drain diode
V
SD
source-drain (diode forward) voltage I
S
= 25 A; V
GS
= 0 V;
Figure 12
-
0.95
1.2
V
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