Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP50N03LT, PHB50N03LT
Logic level FET
PHD50N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
'Trench' technology
V
DSS
= 25 V
Very low on-state resistance
Fast switching
I
D
= 48 A
High thermal cycling performance
Low thermal resistance
R
DS(ON)
16 m
(V
GS
= 10 V)
Logic level compatible
R
DS(ON)
21 m
(V
GS
= 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 'trench' technology.
Applications:-
High frequency computer motherboard d.c. to d.c. converters
High current switching
The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N03LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D
2
PAK)
SOT428 (DPAK)
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j
= 25 C to 175C
-
25
V
V
DGR
Drain-gate voltage
T
j
= 25 C to 175C; R
GS
= 20 k
-
25
V
V
GS
Gate-source voltage (DC)
-
15
V
V
GSM
Gate-source voltage (pulse
T
j
150C
-
20
V
peak value)
I
D
Drain current (DC)
T
mb
= 25 C
-
48
A
T
mb
= 100 C
-
34
A
I
DM
Drain current (pulse peak
T
mb
= 25 C
-
180
A
value)
P
tot
Total power dissipation
T
mb
= 25 C
-
86
W
T
j
, T
stg
Operating junction and
- 55
175
C
storage temperature
d
g
s
1 2 3
tab
1
3
tab
2
1
2
3
tab
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP50N03LT, PHB50N03LT
Logic level FET
PHD50N03LT
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction
-
-
1.75
K/W
to mounting base
R
th j-a
Thermal resistance junction
SOT78 package, in free air
-
60
-
K/W
to ambient
SOT404 and SOT428 packages, pcb
-
50
-
K/W
mounted, minimum footprint
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
W
DSS
Drain-source non-repetitive
I
D
= 25 A; V
DD
15 V;
-
60
mJ
unclamped inductive turn-off
V
GS
= 5 V; R
GS
= 50
; T
mb
= 25 C
energy
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA;
25
-
-
V
voltage
T
j
= -55C
22
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1
1.5
2
V
T
j
= 175C
0.5
-
-
V
T
j
= -55C
-
-
2.3
V
R
DS(ON)
Drain-source on-state
V
GS
= 10 V; I
D
= 25 A
-
13
16
m
resistance
V
GS
= 10 V; I
D
= 25 A (SOT428 package)
-
15
18
m
V
GS
= 5 V; I
D
= 25 A
-
18
21
m
V
GS
= 5 V; I
D
= 25 A; T
j
= 175C
-
-
39
m
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
8
27
-
S
I
DSS
Zero gate voltage drain
V
DS
= 25 V; V
GS
= 0 V;
-
0.05
10
A
current
T
j
= 175C
-
-
500
A
I
GSS
Gate source leakage current V
GS
=
5 V; V
DS
= 0 V
-
10
100
nA
Q
g(tot)
Total gate charge
I
D
= 50 A; V
DD
= 15 V; V
GS
= 5 V
-
17
-
nC
Q
gs
Gate-source charge
-
7.6
-
nC
Q
gd
Gate-drain (Miller) charge
-
11
-
nC
t
d on
Turn-on delay time
V
DD
= 15 V; I
D
= 25 A;
-
6.4
12
ns
t
r
Turn-on rise time
V
GS
= 10 V; R
G
= 5
-
62
75
ns
t
d off
Turn-off delay time
Resistive load
-
50
75
ns
t
f
Turn-off fall time
-
30
45
ns
L
d
Internal drain inductance
Measured tab to centre of die
-
3.5
-
nH
L
d
Internal drain inductance
Measured from drain lead to centre of die
-
4.5
-
nH
(SOT78 package only)
L
s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
1050
-
pF
C
oss
Output capacitance
-
330
-
pF
C
rss
Feedback capacitance
-
220
-
pF
October 1999
2
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP50N03LT, PHB50N03LT
Logic level FET
PHD50N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I
S
Continuous source current
-
-
48
A
(body diode)
I
SM
Pulsed source current (body
-
-
180
A
diode)
V
SD
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
-
0.95
1.2
V
I
F
= 40 A; V
GS
= 0 V
-
1.05
-
t
rr
Reverse recovery time
I
F
= 20 A; -dI
F
/dt = 100 A/
s;
-
100
-
ns
Q
rr
Reverse recovery charge
V
GS
= 0 V; V
R
= 25 V
-
0.13
-
C
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
5 V
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
1
10
100
1000
1
10
100
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
0.01
0.1
1
10
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
October 1999
3
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP50N03LT, PHB50N03LT
Logic level FET
PHD50N03LT
Fig.5. Typical output characteristics
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Fig.8. Typical transconductance
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
0
5
10
15
20
25
30
35
40
45
50
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
2.2 V
2.4 V
Tj = 25 C
VGS = 10 V
3.2 V
2.6 V
4.5 V
2.8 V
3 V
5 V
0
5
10
15
20
25
30
0
5
10
15
20
25
30
35
40
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
175 C
VDS > ID X RDS(ON)
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0
5
10
15
20
25
30
35
40
45
50
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS =4.5 V
10V
Tj = 25 C
2.8V
3 V
2.6 V
2.2 V
2.4 V
3.2 V
5 V
Normalised On-state Resistance
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
Junction temperature, Tj (C)
0
5
10
15
20
25
30
35
40
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
175 C
Threshold Voltage, VGS(TO) (V)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
Junction Temperature, Tj (C)
typical
maximum
minimum
October 1999
4
Rev 1.800
Philips Semiconductors
Product specification
N-channel TrenchMOS
TM
transistor
PHP50N03LT, PHB50N03LT
Logic level FET
PHD50N03LT
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
)
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0
0.5
1
1.5
2
2.5
3
Gate-source voltage, VGS (V)
minimum
typical
maximum
VDS = 5 V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
5
10
15
20
25
30
35
40
45
50
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 50A
Tj = 25 C
VDD = 15 V
100
1000
10000
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
0
5
10
15
20
25
30
35
40
45
50
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
175 C
VGS = 0 V
October 1999
5
Rev 1.800
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